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RISC-V Days Tokyo 2021 Autumn

 

Nov. 17〜19, 2021 / 9:30 〜 15:55 Japan Standard Time (GMT+9)

RISC-V Days Tokyo is Japan’s largest physical and online RISC-V event. On the first day, November 17 (Wed.), presentations and a press conference will be held at Pacifico Yokohama (inside the ET & IoT 2021 exhibition), and the presentation will be broadcast live. On the second and third days, there will be live online presentations. There will also be a “RISC-V Pavilion” for three days. RISC-V Days Tokyo aims to bring together leading RISC-V technologies and products, key persons and engineers, and to provide business opportunities for product recognition, collaboration among companies, technology exchange and information gathering. We look forward to your participation in this opportunity!

Supporter

 

Schedule

DAY 1 : Nov 17th (Wed), 2021 / 10:00 〜 16:45 JST

DAY 2: Nov 18th (Thu), 2021 / 9:30 〜 15:00 JST

DAY 3 : Nov 19th (Fri), 2021 / 9:30 〜 16:15 JST

Online RISC-V Pavilion / Shown Time Slot

DAY 1 : Nov 17th (Wed), 2021 / 10:00 〜 16:45 JST (GMT+9)

LIVE ONLINE BROADCASTING FROM PHYSICAL CONFERENCE

Schedule in Japan Standard Time (GMT+9)
Please note that the speakers and contents are tentative and subject to change, and the schedule may change on the day of the event due to various reasons.

TimeLangPresentation TitleSpeaker | AffiliationMedia
 10:00- 10:15JIntroduction – Conference Q&A Methods and  Online RISC-V Pavilion

#day1_01_intro

Kiyoshi Niwa | DTS INSIGHT, Corp.(Japan)
10:15- 10:30JDAY 1 Welcome

#day1_02_welcome

Hideharu Amano | Science and Technology, Keio University (Japan)PDF

Video

10:30- 11:15JSiFive’s New RISC-V Core Lineup and Case Studies

#day1_03_dts

Atsushi Ishii | SiFive, Inc. / Representative in Japan

Yoshihito Kondo | DTS INSIGHT, Corp. LSI Design Service Dept. (Japan)

Goki Kuroda | ArchiTek Corporation | CMO (Japan)

PDF

Video

11:15- 12:00JAccelerating Machine Learning Workload with High-Performance RISC-V Processor

#day1_04_esperanto

Eiji Kasahara | Esperanto Technologies (USA)PDF

Video

12:00- 13:15JIntermission-Guide to RISC-V PavilionRISC-V Alliance Japan
13:15- 13:50JOutline of TRASIO’s Security system including RISC-V technology

#day1_05_trasio

Daisuke Ito | Technology Research Association of Secure IoT Edge application based on RISC-V Open architecture (TRASIO)/SECOM Intelligent Systems Laboratory Branch/ Researcher (Japan)PDF

Video

13:50- 14:35JRISC-V RTOS Secure IoT

#day1_06_shc

Shumpei Kawasaki | SH Consulting (Japan)PDF

Video

14:35- 15:05JEmbedded RISC-V processor as a part of virtual engine architecture system

#day1_07_architek

Shuichi Takada | ArchiTek Corporation | CEO (Japan)PDF

Video

15:05- 15:15Biological Break 
15:15- 16:00JRISC-V Technological Initiatives within Renesas Electronics Corporation

#day1_08_renesas

Kimiharu Eto | Renesas Electronics Corp. Vice president, MCU product Development DivisionPDF

Video

16:00- 16:30JRISC-V and AI processor Architecture and Implementation on Embedded SoC

#day1_09_nsi

Hideki Sugimoto | NSITEXE Inc.,  | CTO  (Japan)PDF

Video

16:30- 16:45JDAY 1 Closing Remarks

Online RISC-V Pavilion Guide

Day 2 and Day 3 Program Previews

#day1_10_closing

RISC-V Alliance Japan

DAY 2: Nov 18th (Thu), 2021  /  9: 30 〜 15: 00 JST (GMT + 9)

LIVE ONLINE BROADCAST

Schedule in Japan Standard Time (GMT+9)
Please note that the speakers and contents are subject to change, and the time may change on the day of the event due to various reasons.

TimeLangPresentation TitleSpeaker | AffiliationMedia
9:30- 9:40E / JConference Q&A and Online RISC-V Pavilion Guide

#day2_01_intro

Eiji Kasahara | Esperanto Technologies

Kiyoshi Niwa | DTS INSIGHT, Corp.

9: 40- 10: 00JDAY2 Opening Remarks

#day2_02_welcome

Kunio Uchiyama | AIDC (Japan)PDF

Video

10:00- 10:45ERISC-V The Open Era of Computing

#day2_03_riscvi

Calista Redmond | CEO RISC-V International (Switzerland)PDF

Video

10:45- 11:15EAndes RISC-V Processor IP Solutions

#day2_04_andes

Florian Wohlrab | Head of Sales EMEA and Japan, Andes Technology  (Taiwan)Video
11:15- 11:45JIntroduction the GD32VF103 RISC-V based MCU

#day2_05_gigadevice

Ken Kageyama | GigaDevice Japan Co., Ltd.,  Marketing Director (China)PDF

Video

11:45- 12:15JRISC-V Processor development & its extension by ASIP Designer using User RTL

#day2_06_synopsys

Mitsuru Tomono | Solutions Group, Processor & Security IP solutions, Senior Application,  Engineer, Synopsys, Inc. (USA)PDF

Video

12:15- 13:15JIntermission-Conference Q&A and Online RISC-V Pavilion GuideRISC-V Alliance Japan
13:15- 13:45JKhronos Group Digital Standards and Japanese Digital Transformation

#day2_07_khronos

Takashi Umezawa | Khronos Group | NVIDIAPDF

Video

13:45- 14:15
ERISC-V Days Vietnam December 11, 2021 Preview

#day2_08_iti

Xuan-Tu Tran | The Information Technology Institute, Vietnam National University, Hanoi (Vietnam)PDF

Video

14:45- 15:00E / JDay 2 Closing Remarks

Online RISC-V Pavilion Guide

Day 3 Program Previews

#day2_10_closing

RISC-V Alliance Japan

DAY 3 : Nov 19th (Fri), 2021 / 9: 30 〜 15: 45 JST (GMT+9)

LIVE ONLINE BROADCAST

Schedule in Japan Standard Time (GMT+9)
Please note that the speakers and contents are subject to change, and the time may change on the day of the event due to various reasons.

 

 

TimeLangPresentation TitleSpeaker | AffiliationMedia
9:30- 9:45E / JIntroduction – Conference and  Pavilion

#day3_01_intro

Eiji Kasahara | Esperanto Technologies

Kiyoshi Niwa | DTS INSIGHT, Corp.

9:45- 10:00E / JDAY3 Opening Remarks

#day3_02_welcome

Makoto Ikeda | University of Tokyo (Japan)PDF

Video

10:00- 10:45EKhronos Group Presentation

#day3_03_khronos

Neil Trevett | President, Khronos Group | VP Developer Ecosystems, NVIDIAPDF

Video

10:45- 11:15JSDK overview for NSITEXE’s next generation IP

#day3_04_nsi

Seiji Nishimura, Software R&D Project Manager, NSITEXE Inc. (Japan)PDF

Video

11:15- 11:45JStarFive’s CPU Solution

#day3_05_starfive

Masayuki Kimura | Engineer, StarFive (China)No PDF

Video

11:45- 13:00JIntermission-Guide to RISC-V PavilionRISC-V Alliance Japan
13:00- 13:30JIntroducing commercial quality network and security middleware for enabling RISC-V into IoT applications

#day3_06_ubiquitous

Shigeru Kojima | Director, Embedded Platform Division   Ubiquitous AI (Japan)PDF

Video

13:30- 14:00ELinux Distro on RISC-V PC/Server

#day3_07_redhat

Wei Fu | Red Hat Software (Beijing) Co.,Ltd. , Senior Software Engineer (China)PDF

Video

14:00- 14:30EA Design of RISC-V RV32IMAFC Core for MCU as an Opensource IP

#day3_08_maruyama

Munetomo Maruyama | MCU Designer (Japan)PDF

Video

14:30- 15:00JNew FPGA with RISC-V: SLMLET

#day3_09_slmlet

Hideharu Amano, Yosuke Yanai, Akira Okuhara | Keio University, Takuya Kojima | University of Tokyo, Masahiro Iida, Taiki Amagasaki, Morihiro Kuga, Yuya Nakasato | Kumamoto University,
Zhao Ken | Kyushu Institute of Technology
PDF

Video

15:00- 15:30EProcessor IP product line

#day3_10_cloudbear

Alexander Kozlov | CTO, Cloudbear (Russia)PDF

Video

15:30- 16:00ESyntacore Open Source and Processor IP Family

#day3_11_syntacore

Alexander Redkin | Syntacore (Russia)PDF

Video

16:00- 16:30ERVfpga-SoC: How to go from a RISC-V Core to a RISC-V SoC – Education paper

#day3_12_imagination

Zubair Kakakhel | AZKY Tech Limited, on behalf of Imagination Technologies UK.PDF

Video

16:30- 16:45E / JClosing Remarks

Online RISC-V Guide

RISC-V Days Vietnam Preview

#day3_13_closing

RISC-V Alliance Japan

 

Online RISC-V Pavilion

The Online Pavilion provides opportunities for visitors to “see” demos and ask questions through RISC-V a live streaming.

Schedule in Japan Standard Time (GMT+9)  Subject to change

TimeLangTitleCompany / OrganizationMedia
11/17-19

10:00-17:00

JSiFive Update 2021 Autumn

#pavilion_dts

DTS InsightSite
TBDEAndes RISC-V Processor IP Solutions

#pavilion_andes

Andes TechnologyPDF

Video

11/17

12:00-13:15
16:30-17:30

11/18

12:15-13:15
15:00-17:00

11/19

11:45-13:00
15:45-17:00

ERISC-V RoT & OTA Demo

#pavilion_shc

SH Consulting Group

(Vietnam)

PDF

Video

 

RISC-V Publication

The RISC-V Association has campaigned to translate RISC-V publications such as “RISC-V Original” (2018) and “Computer Architecture: Quantitative Approach” (2019).

In 2021, other RISC-V related publications appeared and can be purchased.

In 2021, Chisel study group translated “Digital circuit design starting with Chisel” into Japanese. This will be published by the RISC-V Association.

In the meanwhile we hear Prof. Amano Hideharu of Keio University and his team is planning to translate “Digital Design and Computer Architecture: RISC-V Edition” by Sarah L. Harris, and David Harris We look forward to the completion in 2022.

 

 

About RISC-V Association

RISC-V-logo-figonly-mod-2

RISC-V Association is an association among RISC-V Foundation member companies. RISC-V Foundation defines Member Sponsored Events and Meetups as regional efforts and RISC-V Association supports these events. Presently Software Hardware Consulting handles business ends of this activity.

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