Nov. 17〜19, 2021 / 9:30 〜 15:55 Japan Standard Time (GMT+9)
RISC-V Days Tokyo is Japan’s largest physical and online RISC-V event. On the first day, November 17 (Wed.), presentations and a press conference will be held at Pacifico Yokohama (inside the ET & IoT 2021 exhibition), and the presentation will be broadcast live. On the second and third days, there will be live online presentations. There will also be a “RISC-V Pavilion” for three days. RISC-V Days Tokyo aims to bring together leading RISC-V technologies and products, key persons and engineers, and to provide business opportunities for product recognition, collaboration among companies, technology exchange and information gathering. We look forward to your participation in this opportunity!
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Schedule
DAY 1 : Nov 17th (Wed), 2021 / 10:00 〜 16:45 JST
DAY 2: Nov 18th (Thu), 2021 / 9:30 〜 15:00 JST
DAY 3 : Nov 19th (Fri), 2021 / 9:30 〜 16:15 JST
Online RISC-V Pavilion / Shown Time Slot
DAY 1 : Nov 17th (Wed), 2021 / 10:00 〜 16:45 JST (GMT+9)
LIVE ONLINE BROADCASTING FROM PHYSICAL CONFERENCE
Schedule in Japan Standard Time (GMT+9)
Please note that the speakers and contents are tentative and subject to change, and the schedule may change on the day of the event due to various reasons.
Time | Lang | Presentation Title | Speaker | Affiliation | Media |
---|---|---|---|---|
10:00- 10:15 | J | Introduction – Conference Q&A Methods and Online RISC-V Pavilion | Kiyoshi Niwa | DTS INSIGHT, Corp.(Japan) | |
10:15- 10:30 | J | DAY 1 Welcome | Hideharu Amano | Science and Technology, Keio University (Japan) | |
10:30- 11:15 | J | SiFive’s New RISC-V Core Lineup and Case Studies | Atsushi Ishii | SiFive, Inc. / Representative in Japan Yoshihito Kondo | DTS INSIGHT, Corp. LSI Design Service Dept. (Japan) | |
11:15- 12:00 | J | Accelerating Machine Learning Workload with High-Performance RISC-V Processor | Eiji Kasahara | Esperanto Technologies (USA) | |
12:00- 13:15 | J | Intermission-Guide to RISC-V Pavilion | RISC-V Alliance Japan | |
13:15- 13:50 | J | Outline of TRASIO’s Security system including RISC-V technology | Daisuke Ito | Technology Research Association of Secure IoT Edge application based on RISC-V Open architecture (TRASIO)/SECOM Intelligent Systems Laboratory Branch/ Researcher (Japan) | |
13:50- 14:35 | J | RISC-V RTOS Secure IoT | Shumpei Kawasaki | SH Consulting (Japan) | |
14:35- 15:05 | J | Embedded RISC-V processor as a part of virtual engine architecture system | Shuichi Takada | ArchiTek Corporation | CEO (Japan) | |
15:05- 15:15 | Biological Break | |||
15:15- 16:00 | J | RISC-V Technological Initiatives within Renesas Electronics Corporation | Kimiharu Eto | Renesas Electronics Corp. Vice president, MCU product Development Division | |
16:00- 16:30 | J | RISC-V and AI processor Architecture and Implementation on Embedded SoC | Hideki Sugimoto | NSITEXE Inc., | CTO (Japan) | |
16:30- 16:45 | J | DAY 1 Closing Remarks Online RISC-V Pavilion Guide Day 2 and Day 3 Program Previews | RISC-V Alliance Japan |
DAY 2: Nov 18th (Thu), 2021 / 9: 30 〜 15: 00 JST (GMT + 9)
LIVE ONLINE BROADCAST
Schedule in Japan Standard Time (GMT+9)
Please note that the speakers and contents are subject to change, and the time may change on the day of the event due to various reasons.
Time | Lang | Presentation Title | Speaker | Affiliation | Media |
---|---|---|---|---|
9:30- 9:40 | E / J | Conference Q&A and Online RISC-V Pavilion Guide | Eiji Kasahara | Esperanto Technologies | |
9: 40- 10: 00 | J | DAY2 Opening Remarks | Kunio Uchiyama | AIDC (Japan) | |
10:00- 10:45 | E | RISC-V The Open Era of Computing | Calista Redmond | CEO RISC-V International (Switzerland) | |
10:45- 11:15 | E | Andes RISC-V Processor IP Solutions | Florian Wohlrab | Head of Sales EMEA and Japan, Andes Technology (Taiwan) | Video |
11:15- 11:45 | J | Introduction the GD32VF103 RISC-V based MCU | Ken Kageyama | GigaDevice Japan Co., Ltd., Marketing Director (China) | |
11:45- 12:15 | J | RISC-V Processor development & its extension by ASIP Designer using User RTL | Mitsuru Tomono | Solutions Group, Processor & Security IP solutions, Senior Application, Engineer, Synopsys, Inc. (USA) | |
12:15- 13:15 | J | Intermission-Conference Q&A and Online RISC-V Pavilion Guide | RISC-V Alliance Japan | |
13:15- 13:45 | J | Khronos Group Digital Standards and Japanese Digital Transformation | Takashi Umezawa | Khronos Group | NVIDIA | |
13:45- 14:15 | E | RISC-V Days Vietnam December 11, 2021 Preview | Xuan-Tu Tran | The Information Technology Institute, Vietnam National University, Hanoi (Vietnam) | |
14:45- 15:00 | E / J | Day 2 Closing Remarks Online RISC-V Pavilion Guide Day 3 Program Previews | RISC-V Alliance Japan |
DAY 3 : Nov 19th (Fri), 2021 / 9: 30 〜 15: 45 JST (GMT+9)
LIVE ONLINE BROADCAST
Schedule in Japan Standard Time (GMT+9)
Please note that the speakers and contents are subject to change, and the time may change on the day of the event due to various reasons.
Time | Lang | Presentation Title | Speaker | Affiliation | Media |
---|---|---|---|---|
9:30- 9:45 | E / J | Introduction – Conference and Pavilion | Eiji Kasahara | Esperanto Technologies | |
9:45- 10:00 | E / J | DAY3 Opening Remarks | Makoto Ikeda | University of Tokyo (Japan) | |
10:00- 10:45 | E | Khronos Group Presentation | Neil Trevett | President, Khronos Group | VP Developer Ecosystems, NVIDIA | |
10:45- 11:15 | J | SDK overview for NSITEXE’s next generation IP | Seiji Nishimura, Software R&D Project Manager, NSITEXE Inc. (Japan) | |
11:15- 11:45 | J | StarFive’s CPU Solution | Masayuki Kimura | Engineer, StarFive (China) | No PDF |
11:45- 13:00 | J | Intermission-Guide to RISC-V Pavilion | RISC-V Alliance Japan | |
13:00- 13:30 | J | Introducing commercial quality network and security middleware for enabling RISC-V into IoT applications | Shigeru Kojima | Director, Embedded Platform Division Ubiquitous AI (Japan) | |
13:30- 14:00 | E | Linux Distro on RISC-V PC/Server | Wei Fu | Red Hat Software (Beijing) Co.,Ltd. , Senior Software Engineer (China) | |
14:00- 14:30 | E | A Design of RISC-V RV32IMAFC Core for MCU as an Opensource IP | Munetomo Maruyama | MCU Designer (Japan) | |
14:30- 15:00 | J | New FPGA with RISC-V: SLMLET | Hideharu Amano, Yosuke Yanai, Akira Okuhara | Keio University, Takuya Kojima | University of Tokyo, Masahiro Iida, Taiki Amagasaki, Morihiro Kuga, Yuya Nakasato | Kumamoto University, Zhao Ken | Kyushu Institute of Technology | |
15:00- 15:30 | E | Processor IP product line | Alexander Kozlov | CTO, Cloudbear (Russia) | |
15:30- 16:00 | E | Syntacore Open Source and Processor IP Family | Alexander Redkin | Syntacore (Russia) | |
16:00- 16:30 | E | RVfpga-SoC: How to go from a RISC-V Core to a RISC-V SoC – Education paper | Zubair Kakakhel | AZKY Tech Limited, on behalf of Imagination Technologies UK. | |
16:30- 16:45 | E / J | Closing Remarks Online RISC-V Guide RISC-V Days Vietnam Preview | RISC-V Alliance Japan |
Online RISC-V Pavilion
The Online Pavilion provides opportunities for visitors to “see” demos and ask questions through RISC-V a live streaming.
Schedule in Japan Standard Time (GMT+9) Subject to change
Time | Lang | Title | Company / Organization | Media |
---|---|---|---|---|
11/17-19 10:00-17:00 | J | SiFive Update 2021 Autumn | DTS Insight | Site |
TBD | E | Andes RISC-V Processor IP Solutions | Andes Technology | |
11/17 12:00-13:15 11/18 12:15-13:15 11/19 11:45-13:00 | E | RISC-V RoT & OTA Demo | SH Consulting Group (Vietnam) |
RISC-V Publication
The RISC-V Association has campaigned to translate RISC-V publications such as “RISC-V Original” (2018) and “Computer Architecture: Quantitative Approach” (2019).
In 2021, other RISC-V related publications appeared and can be purchased.
In 2021, Chisel study group translated “Digital circuit design starting with Chisel” into Japanese. This will be published by the RISC-V Association.
In the meanwhile we hear Prof. Amano Hideharu of Keio University and his team is planning to translate “Digital Design and Computer Architecture: RISC-V Edition” by Sarah L. Harris, and David Harris We look forward to the completion in 2022.