at Hitachi BABA Memorial Hall (about 10 min walk from Kokubunji station)
|09:00||Conference Host Announcements||Esperanto Technologies|
|09:15||Expanding Open Innovation at Hitachi||Hitachi Ltd. (Japan), Central Research Laboratory, General Manager|
|09:45||Global Importance and Momentum of RISC-V||RISC-V Foundation（US） CEO|
|10:30||Red Hat RISC-V participation, fedora and firmware development status|
Hennessy and Patterson, Computer Architecture: A Quantitative Approach: Benefits its Japanese Translation Brought and Final 6th Edition
Tokyo University of Agriculture and Technology (Japan) Hironori Nakajo
|11:00||Intermission: Refreshment / Trade Show at Nexperience Room||RISC-V Hennessy and Patterson Quantitative 6J Sale|
|11:30||Taking RISC-V Mainstream from Edge to Cloud||Andes Technology (Taiwan) CTO|
|11:45||Real World Voices of Customers Expectations for RISC-V: Independent System Integrator Speaks||Fujisoft Inc.（Japan)|
Assistant General Manager Distribution Business Section, Embedded Product Business Development Department, Product Business Division
|12:00||RISC-V Based Platform Root of Trust Solutions||Rambus Inc (USA) Senior Manager, Sales|
|12:15||Japan-based RISC-V Promoter Panel Discussion||Keio University|Hideharu Amano (Chair Person),|
AIST|Kuniyasu Suzaki, University of Tokyo|Ryota Shioya, IBM Japan|Seiji Munetoh, University of Electro-Communications, Cong-Kha Pham, SH Consulting KK|Shumpei Kawasaki
|12:50||Venue explanation Hold press conferences (press related only).||Organizer|
|13:00||Lunch: 1st Phase 13: 00 ~ (Even number on last digit of mobile phone number might consider early) 2nd Phase 13: 30 ~ (Odd number on last digit of mobile phone number) . Please pay with the transportation card like “Suica.” No cash or credit card allowed. A trade show will be held at Nexperience Room concurrently. Press Conference in a separate room.||RISC-V version Hennessy and Patterson Quantitative 6J will be sold at discount price at Nexperience Room.|
|14:00||Syntacore 32bit/64bit RISC-V IP Product Line||Syntacore (Russia)|
|14:15||Commercial development environment IAR Embedded Workbench accelerates the introduction of RISC-V processors||IAR (Sweden), Engineering|
|14:30||The Future Created by Big Data in Cars and Edge Computing||Toyota Automotive (Japan), Project General Manager|
|15:00||The Arrival of Humanity Computing -Prospects and Unlimited Potentials for RISC-V-||Ghelia Inc., CEO (Japan)|
|15:15||Leading Semiconductor Design Revolution with SiFive/7-series RISC-V Core IP Enabling Embedded Intelligence||SiFive（USA）Representative in Japan|
|15:30||Embracing a system level approach in the real world: combining ARM and RISC-V in Heterogeneous Designs||UltraSoC（UK） CEO|
|15:45||Intermission: Refreshment / Trade Show at Nexperience Room||RISC-V Hennessy and Patterson Quantitative 6J Sale|
|16:30||Automatic Compiler Generation for RISC-V ISA Customization||Codasip（Czech Republic）|
|16:45||Commercial Grade RTOS “TOPPERS-Pro / ASP” for RISC-V CPUs||Ubiquitous AI Corporation (Japan) |
TOPPERS Business Unit
|17:00||Future of open source EDA tools for FPGA and SoC||Symbiotic EDA (Austria), CEO|
|17:15||RISC-V Hardware security module for IoT devices “CryptoSpec”||SH Consulting Co., Ltd. (Japan) CEO|
|17:30||VDEC, AI Design Center and RISC-V||Professor, University of Tokyo (Japan)|
|17:45||Russian MCU / CPU History: How did we come to adopt RISC-V?||Cloudbear（Russia）|
|18:00||Reception at Nexperience Room: trade show||RISC-V Hennessy and Patterson Quantitative 6J Sale|
|Message from member company Sony to RISC-V and Cheers “Ondo”||Sony LSI Design | Vice President | Hideki Yoshida|
|18:45||Message from Linux Foundation Japan||Linux Foundation Japan | Country Manager | Noriaki Fukuyasu|
|19:00||Message from RISC-V Foundation||RISC-V Foundation (USA) CEO Calista Redmond|
Nidec State-of-the-Art Control System Architecture
|Nidec | Yasushi Fukunaga|
SHC | Shumpei Kawasaki, Esperanto Technologies (USA) | Eiji Kasahara, RISC-Foundation (USA) CEO | Calista Redmond
There are growing momentums around RISC-V in Japan. In 2018, the domestic RISC-V chip projects started at universities and companies. The translated book “RISC-V Reader” was published and became the Amazon best seller. To our pleasure, more than 50 libraries of “Japanese higher professional school specialized vocational high school tertiary colleges,” the cornerstone of Japanese technical education, purchased one or more copies of this publication. At present, SHC, Techanalye, Hitachi, Ltd., NSITEXE (Denso Semiconductor IP Company), Pezy Computing, Sony LSI Design, University of Tokyo, GHELIA, and AIST(Fastest Growing Scientific Research Agency) have become members of RISC-V Foundation. The following is a tentative Presenters and Presentation Topics of “RISC-V Day Tokyo 2019” in English. Subject to update till the Conference ends.
In March 2019, the CHIPS Alliance was launched to host implementation work on RISC-V architecture, and provides design data for RISC-V standard open source computing. Members of the CHIPS Alliance can download code, generate hard logic, run Linux, and provide a fully functional CPU or SoC design with RISC-V. In Japan, the RISC-V Association was launched. It is an informal association of RISC-V Foundation member companies local and overseas to organize affordable RISC-V events both for member companies and attendees. RISC-V Association plans to organize RISC-V domestic events at trade-shows. We believe in wonderful years are coming for hardware system designers. Please look forward to “RISC-V Day Tokyo 2019” held on September 30th. We would appreciate sponsorship and registration for the event. Thank you very much.
Getting to the Venue:
The venue, the Hitachi Baba Memorial Hall, is located within Hitachi Central Research Laboratory. Please walk from Kokubunji Station to the main gate of Central Research Laboratory. There is a RISC-V Day reception tent at the main gate. Our staff will check your registration at the reception tent. Participants should cross the Henjin Bridge, pass Y building, and enter the Collaborative Creation Building. There is Hitachi Baba Memorial Hall in the Collaborative Building. Our staff will give you a name tag. 8 minutes from Kokubunji Station to the main gate of Central Research Laboratory by walk. 8 minutes from the main gate of the Central Research Laboratory to the Kyozo Building.
If you are coming from Kokubunji by taxi or have to come by car, please come from the Central Research Laboratory’s North Gate instead of the Central Research Institute Main Gate (To enter the Baba Memorial Hall by car from the North Gate) Need to enter).
Lunch is from 13:00 to 14:00. As a general rule, please use the Central Research Institute cafeteria. The payment method is only for transportation cards such as watermelon. If you do not have it, please contact the person in charge. In this case, the fee will be paid in cash but rounded up. Lunch is divided into two groups: “13: 00 ~ = Even mobile phone end number even” and “13: 30 ~ = Mobile end number odd”. This is to alleviate the crowded dining room. We realize that this scheme is difficult to enforce. People want to eat with friends, Perhaps you might articulate you have more odd numbers or more even numbers. We hold a trade show in the Nexperience room at lunch time, so if you are not on the turn, please go there.
Reception takes place in the Nexperience room from 18:00 to 20:00.
Information about the participants of this event will be shared with the sponsor. However, if you don’t want to do this, please let us know. EU resident information is required to be managed in accordance with GDPR. Only information with explicit consent will be disclosed to the sponsor.
RISC-V Day Tokyo 2019 will take place at a new Hitachi Baba Memorial Hall. The conference hall opened in April, 2019 and can seats 350 conference attendees. Adjacent “NEXPERIENCE Space,” designed to be used for “Ideathon” and “Hackathon“ serves as a commercial hall for RISC-V demos and electronic poster presentations.
Since its founding in 1910, Hitachi founders dedicated to their innovations for social and information infrastructure betterments. Their venture spirit “Harmony”, “Truthfulness”, and “Patience” need to be passed down to today’s IoT era to renew its commitment to realize human-centered society. Hitachi extends its welcome to all present and future customers and partners from around the world to conduct open collaborative creation with Hitachi researchers and designers.
Prohibited Activities at the Venue：
・ Take pictures outside the authorized place ・ Damage, defacement, or loss of the venue or equipment ・ Inflammables, explosives or other dangerous materials, or those that are unfavorable for hygiene, odors, or others Bringing things that are considered to be harmful to people ・ Singing noise, angry voices, or using violence to cause inconvenience or harm to others ・ Entering facilities other than those that have been approved for use・ Use adjunct facilities ・ Enter with pets other than guide dogs such as guide dogs, nursing dogs, hearing dogs, etc. ・ Smoking, eating and drinking outside designated areas ・ Use open flames・ Attach and post printed materials, advertisements, posters, or similar items other than the designated place ・ Other things that the Company has determined to be administratively problematic
Event Privacy Policies:
We may ask people who have already registered to opt in and opt out of privacy options. At the RISC-V Foundation’s 2015-2017 North American event, it was a default opt-in, and an opt-out if explicitly contacted. The direction of the GDPR (EU’s new data privacy regulations) was enforced on May 25th in the first year of the Ordinance. The concept of the GDPR is that the event host explicitly discloses the handling of the guest data captured at the event, explains the data usage in advance, and obtains the consent of the partner receiving the data. Under the GDPR, if attendees reside in the EU, consent must be obtained even if the data is processed and stored outside the EU. We will follow up on this matter via email, so please understand.
TEN RISC-V News in 2019:
We compiled “Ten RISC-V News for 2019.” I might be wrong about them, and hope you can read it with a generous mind.
1. RISC-V Server 5-year Strategy in Progress:
In June, SiFive, a RISC-V company that raised 12 billion yen in funding, announced that there will be a deployment of commercial RISC-V servers within five years. When such a declaration is made, people jump on the bandwagon in US. The stakeholders in open source community are starting the work it seems to me. RISC-V became a certified Debian-ports architecture in 2019. Server system innovation is currently underway to improve reliability, operation rate, and scalability in server virtualization, container technology, micro service technology, etc. When technology changes, RISC-V can play an active role in the server field. Is done. System Operation Infrastructure Service (IaaS), Application Execution Environment Service (PaaS), Micro Function Service (FaaS), etc. are emerging one after another, and pull requests for full-function serverless RISC-V implementation of OpenFaaS are being merged upstream is. A port of the Kubernetes system written in Google-developed Go language, which facilitates system management and detection, and improves service scalability, is also underway.
2. Enhanced Language Support for RISC-V:
A major foundation of the instruction set (ISA) system is language support. In May, GNU Debugger (GDB) “GDB 8.3”, which supports C, C ++, Ada, Go, and Rust languages, implemented RISC-V support. The (server) system language Go developed by Google is also being ported. Announced that RISC-V will be officially added to the support list in 1.14 when Version 1.13 is released on September 3. It became a big topic. Starting in January, DARPA funding of LLVM / Clang, a new compiler for RISC-V, will start building a foundation for extensive language support across Clang, OpenCL, and Rust. Codasip from the Czech Republic, visiting Japan, is developing a unique and innovative implementation of the jump thread used in the CoreMark benchmark to improve the LLVM solution.
3. RISC-V Breakthrough with Chinese Smartphones:
In the Chinese smartphone field, we announced that Huawei Ascend 910 was developed by ARM with 7nm process as the world’s most powerful AI processor, but announced a 2-CPU strategy that similar chips are also designed by RISC-V. It is. It may be possible in some regions to line up with ARM (currently 99% global share) for both smartphone systems and RISC-V against the backdrop of blocked trade.
4. RISC-V Breakthrough in Flash Microcontrollers and Microcontroller IPs:
The tide of flash microcomputers has changed. The market share of ARM M Series 32-bit MCUs is 15% in 2011, 18% in 2012, and 70% in 2015. Taiwan’s GigaDevice, which has rapidly increased its share in the ARM M series, has declared that it will fully adopt RISC-V. The GD32VF103 series RISC-V MCU has a 153 DMIPS performance at the highest frequency and a 360-point score in the CoreMark benchmark test, 15% faster than its ARM M core. Power consumption is halved.
Following the N8 series developed by Andes Technology against the ARM M series, the RISC-V architecture’s N22 “Bumblebee” IP core is CoreMark / MHz, DMIPS / MHz, CSiBe Code compared to the ARM M series. It is supposed to surpass all the benchmarks of Size.
5. DARPA Security Research Mandates RISC-V:
The DARPA security research project requires the use of RISC-V. DARPA announces SSITH prototype to reduce hardware vulnerabilities. Open source chips are being developed with RISC-V that block the attack and reduce the need for software patches.
6. Creation of RISC-V peripheral integration coalition “Chips Alliance”:
From March, activities such as “Chips Alliance” (FIPS, FOSSi) created by the Linux Foundation under the auspices of Google, etc. have been gathered to integrate IP of peripheral functions that make it easier to create systems with RISC-V. started. Eight core high performance system can be easily created in open source. High-value-added chip products can now be made with open source technology.
7. Open-source EDA tools are Making Huge Advances with RISC-V as Vehicle:
A new generation open source EDA tool is being developed with RISC-V as the vehicle. A new book “Digital Design with Chisel” has been officially published and a new design flow is being established. The existing EDA tools such as Verilator have been widely used, and their reliability, performance, and functions have been drastically improved. Open source EDA tools have been compared to acorns for the past 20 years, but strong contenders have emerged this year. Co-simulation methodologies can now be realized in open source. Because of its simplicity, the FPGA tool Yosys + nexpnr is extremely fast compared to commercial FPGA tools. The FPGA automatic place and route tool nextpnr consists of a device dependent part and a general processing part, and can be mapped to any FPGA by rewriting the device dependent part. Currently, LatticeICE40, ECP5, and Xilinx FPGAs are supported. Open source tools enable a variety of use cases. The “partial configuration function” can be used to test the test vector at high speed in the verification phase. The importance of formal verification is also increasing. Unintentional logic, such as hardware Trojans, can be inserted at multiple points in the development process, but these can be detected with formal verification.
8. RISC-V Influence: Other Open Architecture and Open Source Silicons are Emerging:
nvidia leads NVDLA, an effort to develop an open source machine learning ecosystem. NVDLA Deep Learning Inference Compiler and NVDLA RTL are also available.
The world of servers and CPUs is definitely changing. I don’t know where to settle down. IBM has made the Power architecture free. In accordance with RISC-V, the Power CPU instruction set has been made free. RTL is open sourced. An OpenPower soft core called Microwatt was also announced. A small Open POWER ISA softcore written in VHDL 2008 that aims to be simple and easy to understand. IBM opens OpenPower and supplies power to next-generation chips in China. 19 presentations were presented at the OpenPower Summit in August. . IBM will open source the Power Instruction Set Architecture (ISA), a definition that developers will use to ensure that hardware and software work together on Power. In addition to the Power ISA soft core, OpenCAPI interconnect technology and reference implementations of OMI memory interface technology have also been made open source.
The movement that Wave Computing develops with MIPS Open is modeled on RISC-V.
9. Semiconductor R & D Scope Expanded by RISC-V:
Carbon Nanotube RISC-V Manufacturing Process: Last week, MIT announced a RISC-V CPU made of carbon nanotube (CNT) MOSFETs using materials and processes found in standard CMOS manufacturing facilities and commercial CMOS manufacturing plants. did. With a RISC-V processor that uses carbon nanotube FETs. The energy efficiency is 10 times better.
10. Globalization of RISC-V Organizations and RISC-V Contribution to Free and Open Software and Hardware:
In March, the RISC-V Foundation formed an alliance with the Linux Foundation so that the blockage of trade would not hinder the development of RISC-V. In cooperation with European Free and Open Source Software (FOSS), Free and Open Source Silicon (FOSSi) and other organizations, we were transforming from a simple US organization to a global organization. FOSS and FOSSi appear to us being conducted together as a galvanized monolithic activity like Yin and Yang integrated at their roots via ISA. RISC-V provided one of the centerpieces for FOSS/FOSSi activities originated in Europe. We believe that this activity will make a huge difference in the years to come.
RISC-V Association == Volunteer members of RISC-V Foundation
SH Consulting Co., Ltd .: RISC-V Day Tokyo 2019