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RISC-V Days Tokyo 2022 Spring

Supporter

May 31, 2022 / 12:50 〜 19:00

June 1,  2022 / 10:00 〜 17:00

June 2, 2022 / 10:00 〜 16:00

Japan Standard Time (UTC+9)

RISC-V Days Tokyo is Japan’s largest online RISC-V event.  Live online presentations are hosted on May 31st (Tue), June 1st (Wed) and 2nd (Thu). There will also be a virtual “RISC-V Pavilion” for the last two days. RISC-V Days Tokyo aims to bring together leading RISC-V technologies and products, key persons and engineers, and to provide business opportunities for product recognition, collaboration among companies, technology exchange and information gathering. We look forward to your participation in this opportunity!

Registration (free for online)

Schedule

DAY 1 Conference : May 31st (Tue)  12:50 〜 19:00 JST

DAY 2 Conference : June 1st (Wed) 10:00 〜 16:00 JST

DAY 2 Pavilion: June 1st (Wed) 12:00 〜 13:00 JST

DAY 2 Pavilion: June 1st (Wed) 16:00 〜 17:00 JST

DAY 3 Conference : June 2nd (Thu), 10:00 〜 16:00 JST

DAY 3 Pavilion : June 2nd (Thu), 11:50 〜 13:10 JST

Online RISC-V Pavilion

Asking a Question or Two Making a Comment or Two

    • We are fortunate that this is an online live conference. Our interaction is limited by the 15 second delay in mass transmission to the audience. So questions are raised via chat system of one form or another.
    • If you have any questions or comments about each lecture, please join RISC-V Association Slack enter the slack on #days-tokyo-2022-spring channel !
    • The reason why we recommend slack is due to the time constraints our presenters will not answer all questions or our Q&A staff sometimes miss your question. We do not like to see your brilliant question to be wasted.
    • Ideally please cut and paste presentation hashtag in the timetable below in your Slack entry. This way the presenter will be able to positively identify that your question is for him to answer and likely provide answer via Slack.
    • If you still want to ask questions on Twitter, please tweet with the hashtag attached under the presentation title of the program below. Actually programmer set up a magic. Note question via Twitter will not LAST like Slack but last for some time. Presenter is likely to answer your question here too.
    • If you are logged in as a registered Vimeo user, you can enter comments on Vimeo, but we will not respond to questions or comments at the conference.

Online RISC-V Pavilion Information

Online RISC-V Pavilion

Asking a Question or Two Making a Comment or Two

    • We are fortunate that this is an online live conference. Our interaction is limited by the 15 second delay in mass transmission to the audience. So questions are raised via chat system of one form or another.
    • If you have any questions or comments about each lecture, please join RISC-V Association Slack enter the slack on #days-tokyo-2021-spring channel !
    • The reason why we recommend slack is due to the time constraints our presenters will not answer all questions or our Q&A staff sometimes miss your question. We do not like to see your brilliant question to be wasted.
    • Ideally please cut and paste presentation hashtag in the timetable below in your Slack entry. This way the presenter will be able to positively identify that your question is for him to answer and likely provide answer via Slack.
    • If you still want to ask questions on Twitter, please tweet with the hashtag attached under the presentation title of the program below. Actually programmer set up a magic. Note question via Twitter will not LAST like Slack but last for some time. Presenter is likely to answer your question here too.
    • You can also enter comments on Vimeo if you have logged in as a registered Vimeo user. Beware questions via Vimeo are very very ephemeral and often forgotten after the even tis over.

Demo Booth Information

  • We are offering “ Online RISC-V Pavilion ” as a new attempt to hold online. Interactive demos and Q & A sessions through live streams, as well as individual “private talks (Emails)”, are possible. Please experience this new attempt at RISC-V Day Tokyo!

DAY 1 : May 31st (Tue), 2022 / 12:50 〜 19:00 JST (UTC+9)

Schedule in Japan Standard Time (UTC+9)
Please note that the speakers and contents are tentative and subject to change, and the schedule may change on the day of the event due to various reasons.

TimeLangPresentation TitleSpeaker | AffiliationMedia
12:50-13:00E/JQ&A and  RISC-V Pavilion(Online Booth)

#day1_01_intro

13:00-13:15E/JDAY 1 Welcome Speech:

#day1_02_welcome

Makoto Ikeda | University of Tokyo (Japan)
13:15-14:00JSiFive Update “The future of RISC-V has no limits.”

#day1_03_dtsinsight

Atsushi Ishii | SiFive, Inc. / Representative in Japan

Yoshihito Kondo | DTS INSIGHT, Corp. LSI Design Service Dev. (Japan)

14:00-14:30JARISV-V Processor development & its extension by ASIP Designer using User RTL

#day1_04_synopsys

Mitsuru Tomono | Solutions Group, Processor & Security IP solutions, Staff Application Engineer, Nihon Synopsys G.K. (Japan)
14:30-15:00JIntroducing a New Level of MIPS RISC-V CPU Performance

#day1_05_mips

Michio Abe |  MIPS Tech, Solution Architect (Japan)
15:00-15:30JIntroducing the GD32VF103 RISC-V based MCU

#day1_06_gigadevice

Ken Kageyama | GigaDevice Japan ,  Marketing Director (Japan)
15:30-16:00JAchieving Ultimate Power Efficiency with Efinix FPGAs and the UNO Labo Single-Stage RISC-V Core

#day1_07_efinix

Ikuo Nakanishi | Country Manager, Japan, Effinix (Japan)

Masami Fukushima / UNO Laboratories / President & CEO (Japan)

16:00-16:30JAccelerating RISC-V Software Development with Virtual Prototypes.

#day1_08_esoltrinity

Shuzo Tanaka | VP & Director, Engineering Department , eSOL TRINITY Co.,Ltd.
16:30-17:45JRISC-V high quality verification with new open standard RVVI and ImperasDV

#day1_09_imperas

Shuzo Tanaka | VP & Director, Engineering Department, , eSOL TRINITY Co.,Ltd. (Jpana) /  Imperas Software Ltd.
17:15-17:45ECustom RISC-V solutions from Codasip

#day1_10_codasip

Takaaki Akashi | Japan Country Manager, Codasip (Japan)
17:45-18:15ESoftware development tool that seamlessly supports evaluation, development and functional safety on RISC-V

#day1_11_iar

Naoki Matsuda | Sales Account Manager, IAR Systems (Japan)
18:15-18:45EImagination Catapult: The RISC-V CPU Cores

#day1_12_imagination

Naresh Menon /  Imagination Technologies, Director of Product Management 
18:45-19:00JDAY 1 Closing Remarks

Online RISC-V Pavilion Guide

Day 2 and Day 3 Program Previews

#day1_13_closing

RISC-V Alliance Japan

DAY 2: June 1st (Wed), 2022 / 10:00 〜 16:00 JST (UTC + 9)

Schedule in Japan Standard Time (UTC+9)
Please note that the speakers and contents are subject to change, and the time may change on the day of the event due to various reasons.

TimeLangPresentation TitleSpeaker | AffiliationMedia
10:00-10:05E/JConference Q&A and Online RISC-V Pavilion Guide

#day2_01_intro

10:05-10:40EDAY2 Keynote (Draft title)

#day2_02_riscv

Calista Redmond | CEO RISC-V International (Switzerland)
10:40-11:20ETowards Trustworthy RISC-V Processors for Safety-Critical Applications

#day2_03_siemenseda1

Salaheddin Hetalani | Siemens EDA, Field Application Engineer
11:20-12:00JAlgorithm Acceleration for RISC-V Processors Using Catapult & TLM Modeling

#day2_04_siemenseda2

Kenichi Sakai | Siemens EDA Japan, TSS Calypto Japan, Consultant Application Engineer
12:00-13:00XRISC-V Online Pavilion
13:00-13:30JImpact of Japanese translated version of Harris&Harris’s Digital design and computer architecture RISC-V edition

#day2_05_keio

Hideharu Amano | Professor, Science and Technology, Keio University (Japan)

Mitsugu Suzuki | National Institute of Infectious deseases (Japan)

13:30-14:00JThe AI Edge Contest – Vehicle Driving Image Recognition using RISC-V

#day2_06_signate

Atsuhiro Nishi | SIGNATE Inc., Data Scientist (Japan)
14:00-14:30EIntroduction for Activity of JASA RISC-V WG and Previews of JASA’s 2022 Exhibitions in Osaka and Tokyo

#day2_07_jasa

Tomohisa Kohiyama | JASA RISC-V WG Chief,  JASA (Japan)
14:30-15:00ELinux Distros on RISC-V — status update

#day2_08_redhat

Wei Fu | Red Hat Software (Beijing) Co.,Ltd. , Senior Software Engineer (China)
15:00-15:30EIntroduction to the Codasip University Program

#day2_09_codasip

Keith Graham | Head of University, Codasip
15:30-16:00JDAY 2 Closing Remarks

Online RISC-V Pavilion Guide

Day 3 Program Previews

#day2_10_closing

RISC-V Alliance Japan
16:00-17:00XRISC-V Online Pavilion 

DAY 3 : June 2nd (Thu), 2022 / 10:00 〜 16:00 JST (UTC+9)

Schedule in Japan Standard Time (UTC+9)
Please note that the speakers and contents are subject to change, and the time may change on the day of the event due to various reasons.

TimeLangPresentation TitleSpeaker | AffiliationMedia
10:00-10:05E/JIntroduction – Conference and  Pavilion

#day3_01_intro

Eiji Kasahara | Esperanto Technologies (USA)
10:05-10:30JRecent AI Design Center Activities and Post-Moore Semiconductor Technologies

#day3_02_aist

Kunio Uchiyama | Executive Director, AI Design Center, The National Institute of Advanced Industrial Science and Technology (AIST)
10:30-11:10ELatest Statistics from Google’s No Cost Shuttle Program

#day3_03_google

Tim Ansell | Software Engineer, Google (USA)
11:10-11:50E45 Chips in 30 Days: Open Source ASIC at its best! (Draft title)

#day3_04_efabless

Mohamed Kassem, Chief Technology Officer | eFabless.com (USA)
11:50-13:10XRISC-V Online Pavilion (Virtual Demo Booths)
13:10-13:50JDesigning an Economically Viable SoC using open source EDA,  PDK and IPs – Google’s no-cost shuttle to eFabless shuttle onward

#day3_05_shc

Shumpei Kawasaki | SH Consulting K.K.. Kesami Hagiwara, Pham Cong-Kha | University of Electro-Communications (Japan)
13:50-14:30EInternational Collaboration Opportunity amongst Universities and Research Labs in Asia

#day3_06_iit

Veezhinathan Kamakoti | Director, Indian Institute of Technology Madras( IIT Madras)(India) 
14:30-15:00EOpen source ASIC tooling

#day3_07_zerotoasic

Matt Venn |  Zero to ASIC course, YosysHQ, ChipFlow
15:00-15:30ERISC-V-based System-on-Chip (SoC) Fully Equipped with Cryptographic Accelerators for Transport Layer Security (TLS) 1.3

#day3_08_uec

Trong-Thuc Hoang | Department of Computer and Network Engineering, The University of Electro-Communications,  Assistant Professor
 
Pham Cong-Kha | University of Electro-Communications  (Japan)
15:30-16:00TBDTBD
16:00-16:30XClosing Remarks

RISC-V Days Autumn Preview

#day3_10_closing

RISC-V Alliance Japan

 

Online RISC-V Pavilion

The Online Pavilion provides opportunities for visitors to “see” demos and ask questions through RISC-V a live streaming.

Schedule in Japan Standard Time (UTC+9)  Subject to change

TimeLangTitleCompany / OrganizationMedia
June 1, 12:10-13:00, 15:00-17:00

June 2, 11:50-13:10

EAccelerate Silicon Research with Google Cloud Platform

#pavilion_google

Johan Euphrosine, Google, Developer Relations Engineer (USA)
June 1, 12:10-13:00, 15:00-17:00

June 2, 11:50-13:10

E/JImperas RISC-V virtual prototype booting Zephyr OS and running applications.

#pavilion_esoltrinity

Shuzo Tanaka | VP & Director, Engineering Department , eSOL TRINITY Co.,Ltd.
May 31st 9:00-18:00

Jun 1st 9:00-18:00

Jun 2nd 9:00-18:00

E/JSiFive Update 2022 Spring

#pavilion_dtsinsights

DTS Insights

LSI Design Service Div. Members

June 1, 12:10-13:00, 15:00-17:00

June 2, 11:50-13:10

E/JImperasDV for RISC-V processor hardware design verification.

#pavilion_imperas

Shuzo Tanaka | VP & Director, Engineering Department, , eSOL TRINITY Co.,Ltd.  /  Imperas Software Ltd.
June 1, 12:10-13:00, 15:00-17:00

June 2, 11:50-13:10

EMarmot with digital caliper and OTA

#pavilion_shc

Hoan Huynh Vu | SH Consulting Viet Nam (Viet Nam)

 

RISC-V Publication

The RISC-V Association has campaigned to translate RISC-V publications such as “RISC-V Original” (2018) and “Computer Architecture: Quantitative Approach” (2019).

In 2021, other RISC-V related publications appeared and can be purchased.

In 2021, Chisel study group translated “Digital circuit design starting with Chisel” into Japanese. This will be published by the RISC-V Association.

In the meanwhile we hear Prof. Amano Hideharu of Keio University and his team is planning to translate “Digital Design and Computer Architecture: RISC-V Edition” by Sarah L. Harris, and David Harris We look forward to the completion in 2022.

 

 

About RISC-V Association

RISC-V-logo-figonly-mod-2

RISC-V Association is an association among RISC-V Foundation member companies. RISC-V Foundation defines Member Sponsored Events and Meetups as regional efforts and RISC-V Association supports these events. Presently Software Hardware Consulting handles business ends of this activity.

Recent Posts

  • May 31st-June 2nd “RISC-V Days Tokyo 2022 Spring” event additional information! RISC-V Association decided to release the contents of the program
  • A small company designed and prototyped RISC-V ASIC in 30 days using Google’s sponsored eFabless open source shuttle
  • Feel the Tectonic Shift in Semiconductor Industry at RISC-V Days Tokyo 2022 Online Spring!
  • May 31st to June 2nd, 2022. “RISC-V Days Tokyo 2022 Spring”
  • January 15, 2022 RISC-V Day Vietnam 2022 Presentation Materials are being added now.
  • “RISC-V Vietnam 2022” Saturday, January 15, 2022. Pioneers from Vietnam, India and Japan discuss RISC-V programs.
  • RISC-V Days Vietnam 2021 is Planned on January 15, 2022 Saturday
  • All RISC-V Days Tokyo 2021 Autumn lecture videos are available.
  • Acknowledgements for Participation to RISC-V Days Tokyo 2021 Autumn
  • November 17-19 RISC-V Days: Live online broadcast from ET & IOT venue at Pacifico Yokohama F202 (17th only)

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