Supporter
May 31, 2022 / 12:50 〜 19:00
June 1, 2022 / 10:00 〜 17:00
June 2, 2022 / 10:00 〜 16:00
Japan Standard Time (UTC+9)
RISC-V Days Tokyo is Japan’s largest online RISC-V event. Live online presentations are hosted on May 31st (Tue), June 1st (Wed) and 2nd (Thu). There will also be a virtual “RISC-V Pavilion” for the last two days. RISC-V Days Tokyo aims to bring together leading RISC-V technologies and products, key persons and engineers, and to provide business opportunities for product recognition, collaboration among companies, technology exchange and information gathering. We look forward to your participation in this opportunity!
Schedule
DAY 1 Conference : May 31st (Tue) 12:50 〜 19:00 JST
DAY 2 Conference : June 1st (Wed) 10:00 〜 16:00 JST
DAY 2 Pavilion: June 1st (Wed) 12:00 〜 13:00 JST
DAY 2 Pavilion: June 1st (Wed) 16:00 〜 17:00 JST
DAY 3 Conference : June 2nd (Thu), 10:00 〜 16:00 JST
DAY 3 Pavilion : June 2nd (Thu), 11:50 〜 13:10 JST
Asking a Question or Two Making a Comment or Two
- We are fortunate that this is an online live conference. Our interaction is limited by the 15 second delay in mass transmission to the audience. So questions are raised via chat system of one form or another.
- If you have any questions or comments about each lecture, please join RISC-V Association Slack enter the slack on #days-tokyo-2022-spring channel !
- The reason why we recommend slack is due to the time constraints our presenters will not answer all questions or our Q&A staff sometimes miss your question. We do not like to see your brilliant question to be wasted.
- Ideally please cut and paste presentation hashtag in the timetable below in your Slack entry. This way the presenter will be able to positively identify that your question is for him to answer and likely provide answer via Slack.
- If you still want to ask questions on Twitter, please tweet with the hashtag attached under the presentation title of the program below. Actually programmer set up a magic. Note question via Twitter will not LAST like Slack but last for some time. Presenter is likely to answer your question here too.
- If you are logged in as a registered Vimeo user, you can enter comments on Vimeo, but we will not respond to questions or comments at the conference.
Online RISC-V Pavilion Information
- We are offering “ Online RISC-V Pavilion ” as a new attempt to hold online. Interactive demos and Q & A sessions through live streams, as well as individual “private talks (Emails)”, are possible. Please experience this new attempt at RISC-V Day Tokyo!
DAY 1 : May 31st (Tue), 2022 / 12:50 〜 19:00 JST (UTC+9)
Schedule in Japan Standard Time (UTC+9)
Please note that the speakers and contents are tentative and subject to change, and the schedule may change on the day of the event due to various reasons.
| Time | Lang | Presentation Title | Speaker | Affiliation | Media |
|---|---|---|---|---|
| 12:50-13:00 | E/J | Q&A and RISC-V Pavilion（Online Booth) | ||
| 13:00-13:15 | E/J | DAY 1 Welcome Speech: | Makoto Ikeda | University of Tokyo (Japan) | |
| 13:15-14:00 | J | SiFive Update “The future of RISC-V has no limits.” | Atsushi Ishii | SiFive, Inc. / Representative in Japan Yoshihito Kondo | DTS INSIGHT, Corp. LSI Design Service Dev. (Japan) | |
| 14:00-14:30 | J | ARISV-V Processor development & its extension by ASIP Designer using User RTL | Mitsuru Tomono | Solutions Group, Processor & Security IP solutions, Staff Application Engineer, Nihon Synopsys G.K. (Japan) | |
| 14:30-15:00 | J | Introducing a New Level of MIPS RISC-V CPU Performance | Michio Abe | MIPS Tech, Solution Architect (Japan) | |
| 15:00-15:30 | J | Introducing the GD32VF103 RISC-V based MCU | Ken Kageyama | GigaDevice Japan , Marketing Director (Japan) | |
| 15:30-16:00 | J | Achieving Ultimate Power Efficiency with Efinix FPGAs and the UNO Labo Single-Stage RISC-V Core | Ikuo Nakanishi | Country Manager, Japan, Effinix (Japan) Masami Fukushima / UNO Laboratories / President & CEO (Japan) | |
| 16:00-16:30 | J | Accelerating RISC-V Software Development with Virtual Prototypes. | Shuzo Tanaka | VP & Director, Engineering Department , eSOL TRINITY Co.,Ltd. | |
| 16:30-17:45 | J | RISC-V high quality verification with new open standard RVVI and ImperasDV | Shuzo Tanaka | VP & Director, Engineering Department, , eSOL TRINITY Co.,Ltd. (Jpana) / Imperas Software Ltd. | |
| 17:15-17:45 | E | Custom RISC-V solutions from Codasip | Takaaki Akashi | Japan Country Manager, Codasip (Japan) | |
| 17:45-18:15 | E | Software development tool that seamlessly supports evaluation, development and functional safety on RISC-V | Naoki Matsuda | Sales Account Manager, IAR Systems (Japan) | |
| 18:15-18:45 | E | Imagination Catapult: The RISC-V CPU Cores | Naresh Menon / Imagination Technologies, Director of Product Management | |
| 18:45-19:00 | J | DAY 1 Closing Remarks Online RISC-V Pavilion Guide Day 2 and Day 3 Program Previews | RISC-V Alliance Japan |
DAY 2: June 1st (Wed), 2022 / 10:00 〜 16:00 JST (UTC + 9)
Schedule in Japan Standard Time (UTC+9)
Please note that the speakers and contents are subject to change, and the time may change on the day of the event due to various reasons.
| Time | Lang | Presentation Title | Speaker | Affiliation | Media |
|---|---|---|---|---|
| 10:00-10:05 | E/J | Conference Q&A and Online RISC-V Pavilion Guide | ||
| 10:05-10:40 | E | DAY2 Keynote (Draft title) | Calista Redmond | CEO RISC-V International (Switzerland) | |
| 10:40-11:20 | E | Towards Trustworthy RISC-V Processors for Safety-Critical Applications | Salaheddin Hetalani | Siemens EDA, Field Application Engineer | |
| 11:20-12:00 | J | Algorithm Acceleration for RISC-V Processors Using Catapult & TLM Modeling | Kenichi Sakai | Siemens EDA Japan, TSS Calypto Japan, Consultant Application Engineer | |
| 12:00-13:00 | X | RISC-V Online Pavilion | ||
| 13:00-13:30 | J | Impact of Japanese translated version of Harris&Harris’s Digital design and computer architecture RISC-V edition | Hideharu Amano | Professor, Science and Technology, Keio University (Japan) Mitsugu Suzuki | National Institute of Infectious deseases (Japan) | |
| 13:30-14:00 | J | The AI Edge Contest – Vehicle Driving Image Recognition using RISC-V | Atsuhiro Nishi | SIGNATE Inc., Data Scientist (Japan) | |
| 14:00-14:30 | E | Introduction for Activity of JASA RISC-V WG and Previews of JASA’s 2022 Exhibitions in Osaka and Tokyo | Tomohisa Kohiyama | JASA RISC-V WG Chief, JASA (Japan) | |
| 14:30-15:00 | E | Linux Distros on RISC-V — status update | Wei Fu | Red Hat Software (Beijing) Co.,Ltd. , Senior Software Engineer (China) | |
| 15:00-15:30 | E | Introduction to the Codasip University Program | Keith Graham | Head of University, Codasip | |
| 15:30-16:00 | J | DAY 2 Closing Remarks Online RISC-V Pavilion Guide Day 3 Program Previews | RISC-V Alliance Japan | |
| 16:00-17:00 | X | RISC-V Online Pavilion |
DAY 3 : June 2nd (Thu), 2022 / 10:00 〜 16:00 JST (UTC+9)
Schedule in Japan Standard Time (UTC+9)
Please note that the speakers and contents are subject to change, and the time may change on the day of the event due to various reasons.
| Time | Lang | Presentation Title | Speaker | Affiliation | Media |
|---|---|---|---|---|
| 10:00-10:05 | E/J | Introduction – Conference and Pavilion | Eiji Kasahara | Esperanto Technologies (USA) | |
| 10:05-10:30 | J | Recent AI Design Center Activities and Post-Moore Semiconductor Technologies | Kunio Uchiyama | Executive Director, AI Design Center, The National Institute of Advanced Industrial Science and Technology (AIST) | |
| 10:30-11:10 | E | Latest Statistics from Google’s No Cost Shuttle Program | Tim Ansell | Software Engineer, Google (USA) | |
| 11:10-11:50 | E | 45 Chips in 30 Days: Open Source ASIC at its best! (Draft title) | Mohamed Kassem, Chief Technology Officer | eFabless.com (USA) | |
| 11:50-13:10 | X | RISC-V Online Pavilion (Virtual Demo Booths) | ||
| 13:10-13:50 | J | Designing an Economically Viable SoC using open source EDA, PDK and IPs – Google’s no-cost shuttle to eFabless shuttle onward | Shumpei Kawasaki | SH Consulting K.K.. Kesami Hagiwara, Pham Cong-Kha | University of Electro-Communications (Japan) | |
| 13:50-14:30 | E | International Collaboration Opportunity amongst Universities and Research Labs in Asia | Veezhinathan Kamakoti | Director, Indian Institute of Technology Madras( IIT Madras)（India) | |
| 14:30-15:00 | E | Open source ASIC tooling | Matt Venn | Zero to ASIC course, YosysHQ, ChipFlow | |
| 15:00-15:30 | E | RISC-V-based System-on-Chip (SoC) Fully Equipped with Cryptographic Accelerators for Transport Layer Security (TLS) 1.3 | Trong-Thuc Hoang | Department of Computer and Network Engineering, The University of Electro-Communications, Assistant Professor Pham Cong-Kha | University of Electro-Communications (Japan) | |
| 15:30-16:00 | TBD | TBD | ||
| 16:00-16:30 | X | Closing Remarks RISC-V Days Autumn Preview | RISC-V Alliance Japan |
Online RISC-V Pavilion
The Online Pavilion provides opportunities for visitors to “see” demos and ask questions through RISC-V a live streaming.
Schedule in Japan Standard Time (UTC+9) Subject to change
| Time | Lang | Title | Company / Organization | Media |
|---|---|---|---|---|
| June 1, 12:10-13:00, 15:00-17:00 June 2, 11:50-13:10 | E | Accelerate Silicon Research with Google Cloud Platform | Johan Euphrosine, Google, Developer Relations Engineer (USA) | |
| June 1, 12:10-13:00, 15:00-17:00 June 2, 11:50-13:10 | E/J | Imperas RISC-V virtual prototype booting Zephyr OS and running applications. | Shuzo Tanaka | VP & Director, Engineering Department , eSOL TRINITY Co.,Ltd. | |
| May 31st 9:00-18:00 Jun 1st 9:00-18:00 Jun 2nd 9:00-18:00 | E/J | SiFive Update 2022 Spring | DTS Insights LSI Design Service Div. Members | |
| June 1, 12:10-13:00, 15:00-17:00 June 2, 11:50-13:10 | E/J | ImperasDV for RISC-V processor hardware design verification. | Shuzo Tanaka | VP & Director, Engineering Department, , eSOL TRINITY Co.,Ltd. / Imperas Software Ltd. | |
| June 1, 12:10-13:00, 15:00-17:00 June 2, 11:50-13:10 | E | Marmot with digital caliper and OTA | Hoan Huynh Vu | SH Consulting Viet Nam (Viet Nam) |
RISC-V Publication
The RISC-V Association has campaigned to translate RISC-V publications such as “RISC-V Original” (2018) and “Computer Architecture: Quantitative Approach” (2019).
In 2021, other RISC-V related publications appeared and can be purchased.
In 2021, Chisel study group translated “Digital circuit design starting with Chisel” into Japanese. This will be published by the RISC-V Association.
In the meanwhile we hear Prof. Amano Hideharu of Keio University and his team is planning to translate “Digital Design and Computer Architecture: RISC-V Edition” by Sarah L. Harris, and David Harris We look forward to the completion in 2022.
