Accelerate Silicon Research with Google Cloud Platform
Google, Developer Relations Engineer
|Using the RAD Lab module for Silicon, we ran hundreds of concurrent experiments on Google Cloud to explore the area and density parameter space for a RISC-V core design.|
Between each batch of experiments we reported the estimated total power consumption to the Vertex AI Vizier service, allowing it to suggest new parameters that quickly converge toward the best power metrics for this design.
|SiFive Update 2022 Spring|
ImperasDV for RISC-V processor hardware design verification.
VP & Director
eSOL Trinity Co., Ltd.
Imperas is the leader in RISC-V simulation solutions. For RISC-V processor DV the ‘step-and-compare’ methodology verifies the core RTL against a high-quality reference including asynchronous events and debug operations.
RISC-V custom instruction addition using Codasip Studio
Booth Attendant:Takaaki Akashi | Japan Country Manager, Codasip (Japan)
|Based on our L30 RISC-V core, it is the content to add custom instructions using Codasip Studio (5-10 minutes)|
* We will respond each time you visit us.* Please see the pre-recorded version. Please note that this is not a live demo.* You can select Japanese for YouTube video with subtitles.
Trion / Titanium FPGAs Live Demo
(Trion / Titanium FPGA ライブデモ)
Runs the Efinix Sapphire RISC-V and UNO Labo. 1-stage RISC-V on a Trion FPGA to display biometric information and power consumption.
Titanium FPGA will be conducting real-time image processing and real-time AI object tracking demos.
|Marmot with digital caliper and OTA|
This demonstration shows a full integration of secure OTA firmware upgrade and digital caliper monitor for an IoT with a 32-bit RISC-V running FreeRTOS on Marmot System. In this demonstration the RISC-V RTOS-based IoT conducts OTA via LTE Mobile SIM leveraging Amazon Web Services (AWS) IoT Core.