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RISC-V Days Tokyo 2022 Spring Online RISC-V Pavilion

 


 

 

Accelerate Silicon Research with Google Cloud Platform

Demo PDF Demo Video

 

Booth Attendant:
Johan Euphrosine

Google, Developer Relations Engineer

Using the RAD Lab module for Silicon, we ran hundreds of concurrent experiments on Google Cloud to explore the area and density parameter space for a RISC-V core design.

Between each batch of experiments we reported the estimated total power consumption to the Vertex AI Vizier service, allowing it to suggest new parameters that quickly converge toward the best power metrics for this design.

 

D: PL_TARGET_DENSITY
A: DIE_AREA^mm2
P: TOTAL_POWER

 


 

 

Comprehensive Solutions for RISC-V Architecture form Siemens EDA

Demo introduction site Demo Video

Booth 

Demo introduction site

Booth Attendant:

Yuri Ellison | Marketing Program Manager, Siemens EDA (Japan)

 

 

Siemens EDA offers comprehensive RISC-V solutions including RISC-V integrity verification solution that apply formal verification methodology, DFT solution for silicon debugging and bring-up, and high-level design solution rationing for shift-left in the design cycle, as well as RTOS, middle-ware, IP, tools, and services to enable jump-starting embedded system development.

 


 

 

SiFive Update 2022 Spring Demo Info

Booth Opens:
May 31st 9:00-18:00
Jun 1st 9:00-18:00
Jun 2nd 9:00-18:00

Booth Attendants:
LSI Design Service Div. Members

DTS INSIGHT, Corp.

 SiFive is moving forward faster than ever.

SiFive announced new Performance Family Core “P650” in Dec/2021, incredibly short period from its first Out-of-Order Core P550 release in June/2021.

Not only that, SiFive also introduced new 6-Series in its Essential Family, with 21G3 release which has various improvements in its existing Families.

Even more, SiFive announced Functional Safety adaption for its RISC-V Core, to open the door to Automotive Industry.

We DTS Insight, as SiFive’s Japan distributor, shows these updates in this Virtual Demo Booth.

Go to Demo

 

 


 

Imperas RISC-V virtual prototype booting Zephyr OS and running applications.

Demo Video

Booth Attendant:
Shuzo Tanaka
VP & Director
Engineering Department
eSOL Trinity Co., Ltd.

Imperas is the leader in RISC-V simulation solutions. For RISC-V software development the Imperas technology for virtual platforms allows the development of software before hardware is available. The VAP (Verification, Analysis and Profiling) tools support the separation of running activities to show the low-level firmware, OS processes and application code. In addition, for RISC-V further optimization can be explored with the analysis of custom instructions.
The Imperas models and technology is used to support the Japanese government projects “TRASIO” and “RVSPF” project and a demonstration will be shown with the RISC-V platform booting Zephyr OS and running applications.

 


 

 

 

 

ImperasDV for RISC-V processor hardware design verification.

Demo Video

Booth Attendant:
Shuzo Tanaka
VP & Director
Engineering Department
eSOL Trinity Co., Ltd.

Imperas is the leader in RISC-V simulation solutions. For RISC-V processor DV the ‘step-and-compare’ methodology verifies the core RTL against a high-quality reference including asynchronous events and debug operations.
ImperasDV also supports the open standard RVVI (RISC-V Verification Interface) that covers the RISC-V ISA (Instruction Set Architecture) including privileged mode, vector accelerators, multi hart, multi-cores, as well as custom extensions.
The Imperas RISC-V Reference model can be encapsulated within a UVM test bench and SystemVerilog environment to give a unified debug experience across the RTL and Reference model to enable efficient issue resolution when a discrepancy is found.

 


 

 

RISC-V custom instruction addition using Codasip Studio

Demo PDF Demo Video

Booth Attendant:Takaaki Akashi | Japan Country Manager, Codasip (Japan)
Based on our L30 RISC-V core, it is the content to add custom instructions using Codasip Studio (5-10 minutes)
* We will respond each time you visit us.* Please see the pre-recorded version. Please note that this is not a live demo.* You can select Japanese for YouTube video with subtitles.

 


 

 

Trion / Titanium FPGAs Live Demo

(Trion / Titanium FPGA ライブデモ)

Demo PDF JP Demo PDF EN

Booth Attendant:
Daisuke Sakurada | Efinix Japan / FAE


 

Runs the Efinix Sapphire RISC-V and UNO Labo. 1-stage RISC-V on a Trion FPGA to display biometric information and power consumption.

Titanium FPGA will be conducting real-time image processing and real-time AI object tracking demos.

 


 

Marmot with digital caliper and OTA Demo PDF YouTube Demo Video

Booth Attendant:
Hoan Huynh
Senior Software Engineer, SH Consulting Vietnam Company Limited

 

This demonstration shows a full integration of secure OTA firmware upgrade and digital caliper monitor for an IoT with a 32-bit RISC-V running FreeRTOS on Marmot System. In this demonstration the RISC-V RTOS-based IoT conducts OTA via LTE Mobile SIM leveraging Amazon Web Services (AWS) IoT Core.
Output data from digital caliper is sent to AWS IoT, User can check the data by using PC or Mobile device browser to web app.

 


 

About RISC-V Association

RISC-V-logo-figonly-mod-2

RISC-V Association is an association among RISC-V Foundation member companies. RISC-V Foundation defines Member Sponsored Events and Meetups as regional efforts and RISC-V Association supports these events. Presently Software Hardware Consulting handles business ends of this activity.

Recent Posts

  • On June 20, 2023, the RISC-V Alliance Japan will sponsor Japan’s largest RISC-V conference, “RISC-V Days Tokyo 2023 Summer.” A trade show and poster session will also be held at the same time.
  • RVfpga: Understanding Computer Architecture In-person Workshop 7th and 8th, March ’23
  • RISC-V is expanding in applications from automobiles to enterprises — Commemorating 10 billion RISC-V core shipments — RISC-V JAPAN 2022 product award winners and award ceremony location released
  • HURRY: PACIFICO YOKOHAMA NORTH 3rd Floor G313 Venue map unveiled (RISC-V Days Tokyo 2022 Autumn) November 16-18
  • RISC-V Days Tokyo 2022 Autumn will be broadcasted on November 16-18 at G313 3rd floor Pacifico Yokohama North
  • May 31st-June 2nd “RISC-V Days Tokyo 2022 Spring” event additional information! RISC-V Association decided to release the contents of the program
  • A small company designed and prototyped RISC-V ASIC in 30 days using Google’s sponsored eFabless open source shuttle
  • Feel the Tectonic Shift in Semiconductor Industry at RISC-V Days Tokyo 2022 Online Spring!
  • May 31st to June 2nd, 2022. “RISC-V Days Tokyo 2022 Spring”
  • January 15, 2022 RISC-V Day Vietnam 2022 Presentation Materials are being added now.

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