Hisashi Saito | Ph.D. (Engineering) , Deputy Director / Senior Coordinator | 
Information Industry Division, Commerce and Information Policy Bureau, Ministry of Economy, Trade and Industry (METI)

Mamoru Nakano | President, Tenstorrent Japan

Andrés Lagar-Cavilla | Distinguished Engineer  | Google LLC Mountain View, California, USA

Tomohisa Kohiyama | Chief Officer, RISC-V Working Group, Japan Embedded Systems Technology Associations (JASA)   | Business Management Department, Infrastructure Systems Division / Quality Assurance Division, Hitachi Industrial Equipment Systems Co., Ltd.

Yoshitaka Kurokawa | Member, RISC-V Working Group, Japan Embedded Systems Technology Association (JASA)

Nobumori Nakajima | Semiconductor Design Department 1, Digital Infrastructure Solutions Division, Hitachi Industrial Control Solutions, Ltd. (HiICS)

Masataka Kobayashi | RISC-V Working Group, Japan Embedded Systems Technology Associations (JASA)  | Semiconductor Design Department 1, Digital Infrastructure Solutions Division, Hitachi Industrial Control Solutions, Ltd. (HiICS) (with one additional member)

Japan’s Semiconductor Strategy 2025 | Commerce and Information Policy Bureau, Ministry of Economy, Technology and Industry
This presentation outlines Japan’s Semiconductor Strategy 2025, an initiative led by METI to rebuild Japan’s semiconductor ecosystem and enhance its role in global supply chains. Amid rapid digital transformation and intensifying concerns over economic security, the strategy seeks to strengthen Japan’s technological base through collaboration among industry, academia, and government. Its priorities include: Reinforcing R&D and manufacturing capabilities for next-generation semiconductors and advanced packaging, Expanding digital and AI infrastructure to meet growing data and computing demands, and Cultivating talent and innovation ecosystems in both hardware and software. Rather than a single industrial policy, the initiative reflects Japan’s broader commitment to secure, sustainable, and globally connected semiconductor development—anchored in partnerships with like-minded economies and the private sector.

Scaling Open Compute: RISC-V, Chiplets, and the Future of AI and Robotics | Mamoru Nakano | President, Tenstorrent Japan
As artificial intelligence and autonomous systems become pervasive, compute diversity and openness are key to sustainable scaling. This talk presents Tenstorrent’s vision for open, high-performance computing built on RISC-V and chiplet-based architectures.
Tenstorrent introduces its Ascalon and Callandor RISC-V cores, designed for world-class SPEC performance, and Ascalon-Auto, an ISO 26262-compliant processor for automotive and robotic applications. These CPUs integrate with Tensix AI accelerators in modular chiplet configurations that scale from edge to data center.
A core part of this strategy is the Open Chiplet Architecture (OCA)—a layered standard that unifies physical, transport, protocol, system, and software interfaces—enabling interoperable, multi-vendor silicon ecosystems.
By combining openness, scalability, and performance, Tenstorrent positions RISC-V as a credible alternative to proprietary architectures, empowering the next generation of AI-enabled and autonomous systems across cloud, robotics, and automotive domains.

Caliptra and OpenTitan Tutorial  | Andrés Lagar-Cavilla | Google LLC Mountain View, California, USA
This tutorial will focus on Caliptra, an open Root of Trust (RoT) project under the Open Compute Project (OCP) led by Google, Microsoft, AMD and Nvidia, and supported by semiconductor companies such as Nuvoton, Samsung and Intel, as well as on OpenTitan, an independent RoT chip initiative led by Google and now being mass-produced by Nuvoton.

Caliptra is designed as an SoC-embedded stack that includes firmware, provisioning, and Linux integration, whereas OpenTitan aims to provide a standalone security chip. While OpenTitan represents a transparent, discrete RoT implementation, Caliptra targets the standardization of integrated RoT solutions for cloud and datacenter systems. This session will explore both projects’ design philosophies, secure boot mechanisms, and approaches to improving trust through open-source development.

Designing Agentic Loops that Actually Ship— Practical Frameworks for Building Reliable AI Agents in Robotics and Production Systems  | Chirag Agrawal | Senior Software Engineer | Amazon.com, Inc.
Agentic AI systems are closed-loop programs that can reason, plan, invoke tools, evaluate results, and iterate autonomously until a goal is achieved. However, making these systems production-ready requires engineering discipline across latency, cost, privacy, and reliability.
This talk presents a practical framework for designing and deploying agentic AI loops at scale. The session explores how the ReAct (Reason + Act) paradigm enables robust tool-based agents and multi-agent collaboration, emphasizing tool routing policies, context compression, and on-device retrieval techniques that balance privacy and performance.
As cloud-based AI systems encounter limits in responsiveness and data protection, Chirag discusses how RISC-V–based and chiplet-driven platforms are opening new frontiers for local autonomy—enabling intelligent agents to reason, learn, and operate directly on edge and robotic systems.
Attendees will gain engineering blueprints and operational guardrails for building sustainable, self-improving AI agents across cloud, edge, and robotics domains, along with insights into how open hardware like RISC-V can power the next generation of scalable, trustworthy AI infrastructure.

Activities of RISC-V Working Group of JASA RISC-V Working Group  | RISC-V Working Group, Japan Embedded Systems Technology Associations (JASA)
In recent years, the JASA RISC-V Working Group, efforts have focused on promoting understanding of RISC-V and validating implementation technologies.

The group first implemented a RISC-V processor on FPGA, followed by a prototype chip fabricated through the Google Shuttle program, on which functional demonstrations and software evaluations were conducted.

Currently, the group is developing an original in-house RISC-V chip design, achieving successful demonstrations at each stage.

This presentation will highlight these achievements and discuss future development plans.

Prototyping a Custom RISC-V CPU IP and Chip Using TinyTapeout | Yoshitaka Kurokawa | Member, RISC-V Working Group, Japan Embedded Systems Technology Association (JASA)
Because TinyTapeout imposes strict limits on the logic capacity available per design, a standard 5-stage RISC architecture would far exceed the allowable size.
In this study, the instruction set was preserved while the CPU was redesigned into a state-machine architecture, reducing the logic area to one-quarter of the original and enabling the logical design of a RISC-V-compatible CPU capable of running FreeRTOS.
This presentation reports on the development process and optimization techniques used to create a RISC-V-compatible CPU suitable for submission to the TinyTapeout shuttle.

Development of a RISC-V CPU IP and Chip Using Open-Source IP, PDK, and EDA | Nobumori Nakajima | Semiconductor Design Department 1, Digital Infrastructure Solutions Division, Hitachi Industrial Control Solutions, Ltd. (HiICS)
Hitachi Industrial Control Solutions, Ltd. aims to revitalize Japan’s domestic semiconductor market by leveraging its expertise in semiconductor design integration and promoting in-house custom chip design.
In this presentation, the company introduces its efforts to prototype a RISC-V microcontroller using chipIgnite, a service provided by ChipFoundry, along with open-source RISC-V core IPs and design platforms.
During the prototyping process, the team encountered challenges unique to open-source development—such as toolchain preparation, layout design, and verification environment setup. To address these, they implemented practical measures including reusing design assets and clarifying the applicability of open-source tools.
This presentation shares key insights gained through the design and verification process and highlights the emerging possibilities of semiconductor development leveraging open-source IP, PDKs, and EDA tools.

Practical Evaluation and Reproducibility Verification of a RISC-V CPU Chip— JASA Open Platform Development Using FPGA and Google Open MPW —Masataka Kobayashi | RISC-V Working Group, Japan Embedded Systems Technology Associations (JASA)  | Semiconductor Design Department 1, Digital Infrastructure Solutions Division, Hitachi Industrial Control Solutions, Ltd. (HiICS) 
The JASA RISC-V Working Group (WG) is advancing the adoption and implementation capabilities of RISC-V in the embedded systems domain by developing an open RISC-V platform that members can freely utilize under open specifications.
This evaluation project aims to systematically verify the reproducibility, portability, and verifiability of a RISC-V CPU subsystem using both FPGA and the Open MPW (eFabless) fabrication flow.
The first phase involves booting 64-bit Linux on the Arty A7-100T FPGA board using LiteX + RocketChip, standardizing the SoC integration, build procedure, and environment requirements to establish a baseline for RISC-V software and toolchain readiness.
The second phase evaluates the feasibility of realizing a JASA-developed chip by implementing user logic and validating debugging features on the Caravel Open MPW harness. This includes confirming the operation of the “Marmot1” logic within an MPW-6-class area, documenting test procedures, and ensuring the reusability of results.
The team also addresses practical engineering challenges such as dependency resolution during reproduction of the frozen SiFive Freedom repositories, Docker-based reproducibility improvements, and fixing older toolchains (e.g., RISC-V toolchain v2020.12) to ensure consistent rebuilds. These efforts will be published as a publicly accessible reproduction guide (How-to) that can be followed even by teams outside JASA.

Hisashi Saito, Ph.D. (Engineering) | Deputy Director, Information Industry Division, Commerce and Information Policy Bureau, Ministry of Economy, Trade and Industry (METI), Japan
Dr. Hisashi Saito serves as Deputy Director at the Information Industry Division of METI’s Commerce and Information Policy Bureau. Before joining METI in 2021, he spent over a decade in the private sector engaged in semiconductor research and development, particularly in process and manufacturing technologies. Since entering government service, he has been deeply involved in formulating Japan’s semiconductor and digital industry strategies, including initiatives for advanced-node (2 nm-class) technology promotion and domestic manufacturing site attraction. Academically, Dr. Saito holds a Ph.D. in Engineering and has published several papers on semiconductor device physics, such as studies on reducing output conductance in vertical InGaAs channel MOSFETs. Drawing on his dual background in advanced R&D and industrial policy, he plays a vital role in bridging technology development and national strategy to revitalize Japan’s semiconductor and electronics ecosystem.

Mamoru Nakano | President, Tenstorrent Japan
Mamoru Nakano is a veteran of the semiconductor, HPC, and AI/ML industries with more than three decades of leadership experience across Japan, the U.S., and the Asia-Pacific region. He currently serves as President and Representative Director of Tenstorrent Japan Inc., the Japanese subsidiary of Canada-based Tenstorrent Inc., founded in January 2023 to expand the company’s AI computing business in Japan.
Before joining Tenstorrent, Mr. Nakano served as Country Manager of Graphcore Japan, where he led sales, marketing, and customer engagement for AI processors and systems. Prior to that, he was President of Cray Japan Inc. for over 16 years, spearheading the company’s HPC business and market growth in Japan and Asia. Earlier in his career, he held executive roles at Hewlett-Packard, including General Manager of HPC and Linux Business for Asia-Pacific, overseeing regional strategy and operations.
At Tenstorrent Japan, Mr. Nakano leads the company’s efforts to deliver AI accelerators, RISC-V processors, and chiplet-based architectures to Japanese partners across academia, industry, and government. Under his leadership, Tenstorrent Japan is advancing Japan–U.S. technology collaboration under NEDO initiatives, contributing to the development of an open, trusted, and scalable digital infrastructure for next-generation AI and robotics.

Andrés Lagar-Cavilla | Distinguished Engineer  | Google LLC Mountain View, California, USA| Google LLC Mountain View, California, USA
Dr. H. Andrés Lagar-Cavilla is a Principal Engineer at Google, where he leads efforts at the intersection of open hardware security and confidential computing. Within the Open Compute Project (OCP), he serves as one of Google’s principal technical representatives, shaping the direction of the Open Compute Security Project (OCSP) and the Data Center Secure Control Module (DC-SCM) specifications. Through this work, he defines how open server architectures implement a consistent Root of Trust, secure boot, and attestation framework across hyperscale systems. At Google, Andrés drives the integration of platform-level trust mechanisms—from DC-SCM’s hardware-anchored security to higher-layer HSM services and confidential computing environments—to establish verifiable end-to-end protection for data in use. His leadership ensures that Google’s internal infrastructure and the broader OCP ecosystem advance together toward transparent, interoperable, and cryptographically verifiable security foundations. By bridging open standards and production-scale systems, Andrés continues to redefine how modern data centers achieve trust by design.

Chirag Agrawal | Senior Software Engineer | Amazon.com, Inc., Seattle, Washington, USA
Chirag Agrawal is a senior software engineer at Amazon who has contributed to the engineering foundations behind next-generation conversational-AI systems such as Alexa+.
He has built mission-critical infrastructure, including the conversational-memory backbone and the RAG-based Bring-Your-Own-Content (BYOC) pipeline — foundational systems that power Amazon’s multi-agent, reasoning-driven architecture.
His work spans real-time context compression, prompt optimization, and retrieval-augmented interaction frameworks, all designed to enhance latency, reliability, and scalability across production-grade intelligent agents.
Chirag’s current research explores how agentic AI loops can achieve autonomy beyond the cloud, leveraging RISC-V–based and chiplet-driven platforms to bring reasoning and learning directly to edge and robotic systems.
This pursuit reflects his broader vision of scalable, privacy-first, and self-improving AI infrastructure that bridges cloud-edge boundaries.
He has been featured on InfoQ and leading AI-engineering podcasts for his work on practical frameworks for deploying sustainable agentic AI systems.
At RISC-V Day Tokyo 2025 Autumn, he presents “Designing Agentic Loops that Actually Ship — Practical Frameworks for Building Reliable AI Agents in Robotics and Production Systems.”

Tomohisa Kohiyama | Chief, JASA RISC-V Working Group | Hitachi Industrial Equipment Systems Co., Ltd., Hitachi Industrial Equipment Systems Co., Ltd., Infrastructure Systems Division, Business Management Department / Quality Assurance Division
Tomohisa Kohiyama serves as the Chief of the JASA RISC-V Working Group, leading Japan’s industrial initiatives for the promotion and standardization of RISC-V in embedded systems.
He is a Principal Engineer at Hitachi Industrial Equipment Systems Co., Ltd., where he works under the Infrastructure Systems Division, Business Management Department, and Quality Assurance Division. His professional focus lies in enhancing the reliability and quality assurance of embedded systems for social and industrial infrastructure applications. Mr. Kohiyama is a Professional Engineer (P.E. Jp) certified in Electrical & Electronics Engineering, Information Engineering, and Comprehensive Technical Management, and he is also recognized as an IEEE Wireless Communications Professional.

Yoshitaka Kurokawa | Member, RISC-V Working Group, Japan Embedded Systems Technology Association (JASA)
He works for a manufacturing company and has professional experience in digital semiconductor circuit design.
A long-time electronics hobbyist, he has developed various projects using Raspberry Pi.
During the COVID-19 pandemic, he began building his own RISC-V CPU using FPGA.
He is currently developing a custom 5-stage RISC-V processor while also designing a lightweight CPU for Tiny Tapeout and conducting functional verification on FPGA.

Nobumori Nakajima | Semiconductor Design Department 1, Digital Infrastructure Solutions Division, Hitachi Industrial Control Solutions, Ltd. (HiICS)
Since 2004, he has been engaged in chip development for embedded systems, including DSPs, FPGAs, storage controller ASICs, and automotive microcontrollers.
He is currently leading the prototyping and verification development of RISC-V microcontrollers.

Masataka Kobayashi | Semiconductor Design Department 1, Digital Infrastructure Solutions Division, Hitachi Industrial Control Solutions, Ltd. (HiICS) (with one additional member)
Until 2023, he spent over 30 years engaged in embedded system software design, working on platforms such as Windows CE and Android.
Since 2023, he has been an active member of the RISC-V Working Group under the Japan Embedded Systems Technology Association (JASA), contributing to initiatives aimed at developing JASA’s own RISC-V chip.
In the Tiny Tapeout project, he was responsible for evaluating the RISC-V chip designed by Mr. Kurokawa, conducting functional verification and reproducibility testing of the toolchain.
Currently, he is working on establishing a lightweight SoC design and verification flow using open-source EDA tools, as well as developing educational and research-oriented RISC-V design environments.

Noritsuna Imamura | ISHI-Kai | OpenSUSI
Inspired by participation in the IPA Unexplored Software Project, the speaker became deeply involved in open-source development. Through helping to establish the Japan Java Users Group and the Japan Android Group, he contributed significantly to the growth of Japan’s open-source software community. Later, while engaged in space development and small satellite design, he recognized the need for the mass production and democratization of hardware. Together with Professor Tsuchiya of The University of Shiga Prefecture, he founded the open-source semiconductor community “ISHI-Kai.” Today, he promotes open hardware design education for the RISC-V era through initiatives such as Tiny Tapeout.