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Presentation Title
Abstract

Speaker
Bio

9:30-17:50

Moderator

Tomohisa Kohiyama | Chief, RISC-V Working Group, Japan Embedded Systems Technology Associations (JASA) | Chief Engineer, Infrastructure Systems Group, Hitachi Industrial Equipment Systems Co., Ltd.
As the chair of the JASA RISC-V Working Group, Tomohisa leads RISC-V adoption and standardization efforts within Japan’s embedded software industry. He currently serves as a Senior Chief Engineer in both the Business Management Department and the Quality Assurance Department of the Infrastructure Systems Division at Hitachi Industrial Equipment Systems Co., Ltd., where he focuses on improving the quality and reliability of embedded systems, particularly in the social infrastructure domain.

9:40-10:00Video
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Welcome Remark: “Research and Innovation in RISC-V”
The presentation will give an explanation on practical educational approaches for training the next generation of semiconductor engineers using open technologies.

Makoto Ikeda | Professor, Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo
Prof. Ikeda conducts a wide range of research, including semiconductor and AI hardware, hardware security, high-performance computing, and secure sensing.

10:00-10:20Video
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Japan’s Semiconductor and Digital Industry Strategy
Semiconductors are a key technology that plays an essential role in both digital transformation (DX) and green transformation (GX). In 2021, the Ministry of Economy, Trade and Industry (METI) formulated the “Semiconductor and Digital Industry Strategy,” and has since continued to convene the Semiconductor and Digital Industry Strategy Review Committee on an ongoing basis.
This presentation will provide an overview of Japan’s latest semiconductor and digital industry strategy, focusing in particular on the major policies and initiatives related to the semiconductor sector.

Hisashi Saito | Ph.D. (Engineering) , Deputy Director / Senior Coordinator | Information Industry Division, Commerce and Information Policy Bureau, Ministry of Economy, Trade and Industry (METI)
Hisashi is committed to revitalizing Japan’s semiconductor and electronics industries by advancing technology development and industrial promotion in an integrated manner. He spent nearly a decade in the private sector He is committed to revitalizing Japan’s semiconductor and electronics industries by advancing technology development and industrial promotion in an integrated manner. He spent nearly ten years in the private sector engaged in semiconductor R&D, gaining extensive experience in manufacturing and process technologies. Since joining the Ministry of Economy, Trade and Industry (METI) in 2021, he has played a central role in shaping Japan’s semiconductor and digital industry strategies, attracting domestic and international manufacturing bases, and supporting semiconductor technology development—serving as a key contributor to Japan’s national semiconductor policy.

10:30-10:50Video
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Introduction to High-Performance Connectivity IP by Alphawave Semi
This talk introduces Alphawave Semi’s chiplet reference architecture, which integrates the company’s IP offerings across multiple foundries. It also explains the company’s die-to-die (D2D) interconnect IP technology and its next-generation 224G high-speed connectivity IP, which support both scale-up and scale-out strategies.

Sue Hung Fung | Product Line Manager, Principal IP Group Product Marketing, Alphawave Semi
Ms. Fung has over 20 years of experience in chip/chiplet connectivity IP, memory subsystem IP, and mixed-signal IP, and is highly regarded for her ability to combine deep IP expertise with strong product strategy execution. Her career spans IP development, memory interfaces, chiplet interconnects, and mixed-signal IP, with roles at Cadence Design Systems, Analog Bits, Kilopass Technology (now part of Synopsys), and Google.

11:00-11:30
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Cheol Kim| Director of Product Marketing, MIPS Technologies
Cheol Kim is Director of Business Development for MIPS, a GlobalFoundries company. MIPS is the #1 RISC-V IP provider for physical AI, delivering processor IP for autonomous machines like robotics, automotive, and industrial applications. Cheol is an experienced technology leader with expertise in edge AI, IoT, embedded, automotive, and communications infrastructure markets. Cheol is a graduate of Havard Business School (Executive MBA); Temple University (MBA); University of Oregon (Bachelor of Science); Meiji Gakuin University (Bachelor of Arts). He has more than 30 years experience, with roles at Thundersoft, Intel, Schleuniger Global, Rimnet, and LG.

11:40-12:00
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Kuniyasu Suzaki | Institute of Information Security
Kuniyasu withdrew from the doctoral program at Tokyo University of Agriculture and Technology in 1991 and joined the Electrotechnical Laboratory of the Agency of Industrial Science and Technology, Ministry of International Trade and Industry, in the same year. From 1997 to 1998, he served as a visiting researcher at the Australian National University. In 2001, following organizational restructuring, he became part of the National Institute of Advanced Industrial Science and Technology (AIST). In the same year, he was a visiting researcher at the University of Illinois at Urbana–Champaign. He received his Ph.D. in Information Science and Technology from the University of Tokyo in 2009. He has been a professor at his current institution since September 2022. He is a member of IPSJ, IEICE, and IEEE, and received the IPA Japan OSS Contributor Award in 2010.

 12:10-12:40
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Andrés Lagar-Cavilla | Distinguished Engineer  | Google LLC Mountain View, California, USA
Dr. H. Andrés Lagar-Cavilla is a Principal Engineer at Google, where he leads efforts at the intersection of open hardware security and confidential computing. Within the Open Compute Project (OCP), he serves as one of Google’s principal technical representatives, shaping the direction of the Open Compute Security Project (OCSP) and the Data Center Secure Control Module (DC-SCM) specifications. Through this work, he defines how open server architectures implement a consistent Root of Trust, secure boot, and attestation framework across hyperscale systems. At Google, Andrés drives the integration of platform-level trust mechanisms—from DC-SCM’s hardware-anchored security to higher-layer HSM services and confidential computing environments—to establish verifiable end-to-end protection for data in use. His leadership ensures that Google’s internal infrastructure and the broader OCP ecosystem advance together toward transparent, interoperable, and cryptographically verifiable security foundations. By bridging open standards and production-scale systems, Andrés continues to redefine how modern data centers achieve trust by design.

14:00-14:30
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 14:40-15:10
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 15:20-15:50
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Tomohisa Kohiyama | Chief, RISC-V Working Group, Japan Embedded Systems Technology Associations (JASA) | Chief Engineer, Infrastructure Systems Group, Hitachi Industrial Equipment Systems Co., Ltd.
As the chair of the JASA RISC-V Working Group, Tomohisa leads RISC-V adoption and standardization efforts within Japan’s embedded software industry. He currently serves as a Senior Chief Engineer in both the Business Management Department and the Quality Assurance Department of the Infrastructure Systems Division at Hitachi Industrial Equipment Systems Co., Ltd., where he focuses on improving the quality and reliability of embedded systems, particularly in the social infrastructure domain.
Yoshitaka Kurokawa | RISC-V Working Group, JASA
Yoshitaka works for a manufacturing company and has prior experience in semiconductor digital circuit design. A long-time electronics enthusiast, he has developed various projects using Raspberry Pi. During the COVID-19 pandemic, he began building his own RISC-V CPUs on FPGA. He is currently developing a custom 5-stage RISC-V processor and designing a lightweight CPU for Tiny Tapeout, with functional verification underway on FPGA.
Masataka Kobayashi | RISC-V Working Group, JASA  | Semiconductor Design Department 1, Digital Infrastructure Solutions Division, Hitachi Industry & Control Solutions, Ltd. (HiICS)
Until 2023, Masataka spent more than 30 years engaged in embedded system software development, including Windows CE and Android–based systems. Since 2023, he has been a member of the JASA RISC-V Working Group, contributing to efforts toward developing JASA’s own RISC-V chips. In the Tiny Tapeout project, he was responsible for evaluating the RISC-V chip designed by Mr. Kurokawa, performing functional verification and confirming toolchain reproducibility. He is currently working on establishing a verification flow for small-scale SoC design using open-source EDA tools and developing RISC-V design environments for education and research.
Shumpei Kawasaki | SH Consulting K.K. 
Shumpei is an engineer and advocate serving as the Representative Director of the RISC-V Association in Japan. Through the promotion of open instruction set architectures such as RISC-V and open semiconductor technologies, he aims to strengthen Japan’s semiconductor capabilities and expand design freedom.

 16:00-16:20
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16:50-17:00

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Open Architecture Lightening Talk ①
RISC-V SoC Design Using Open-Source IP, PDK, and EDA
This presentation introduces our effort to prototype a RISC-V microcontroller using the “chipIgnite” service from chipfoundry, along with open-source RISC-V core IP and design platforms. During the prototyping process, we encountered a number of challenges unique to open-source development—including toolchain preparation, layout design, and verification environment construction. To address these issues, we applied practical approaches such as reusing design assets and clearly defining the applicable scope of open-source tools. This talk shares the insights gained in establishing a design and verification flow through this process and highlights new possibilities for semiconductor development using open-source technologies.

Nobushige Nakajima | Semiconductor Design Department 1, Digital Platform Solution Division, Hitachi Industry & Control Solutions, Ltd. (HiICS)
Since 2004, he has been engaged in chip development for embedded systems, including DSPs, FPGAs, storage-control ASICs, and automotive microcontrollers. He is currently leading the prototyping and verification of RISC-V microcontrollers.

17:05-17:15
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Open Architecture Lightening Talk ②
CHERI ALLIANCE 101
This lightning talk provides an introduction to the CHERI (Capability Hardware Enhanced RISC Instructions) security architecture and the role of the CHERI Alliance in promoting its global adoption. CHERI extends conventional ISAs with hardware-enforced capability-based memory protection, enabling fine-grained, efficient prevention of common security vulnerabilities (e.g. buffer overflows, out-of-bounds memory access) while maintaining compatibility with legacy C/C++ code.
We will highlight how Codasip is implementing CHERI on RISC-V, providing a fully functional CHERI-enabled core and a corresponding open-source SDK donated to the CHERI Alliance for community use.

Takaaki Akashi｜Country Manager – Codasip Japan
Takaaki Akashi was appointed Japan Country Manager of Codasip GmbH in April 2022, coinciding with the establishment of the company’s Japanese subsidiary. Since then, he has led Codasip’s business expansion and organizational development in the Japanese market. Akashi has built a career of more than 25 years in the semiconductor design and EDA industries. In his previous roles at Synopsys and Cadence Design Systems, he was responsible for high-level customer engagement and technical marketing, gaining extensive experience and deep expertise in the field. In the 1990s, he played a key role in the early adoption of Verilog in Japan, and in the early 2000s he contributed to the spread of SystemVerilog, helping advance the adoption of HDL and foundational design technologies nationwide.

17:20-17:30 Video
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Open Architecture Lightening Talk ③
A Rapid Tour of Various Open PDKs / EDA Tools
Japan’s semiconductor workforce has shrunk by roughly 30% over the past 20 years, and the number of employees in the integrated circuit manufacturing sector is said to have dropped drastically—from around 150,000 in 1999 to about 60,000 in 2023. Developing semiconductor engineers requires many years, and mastering the processes of design, manufacturing, and evaluation demands extensive hands-on experience.
However, commercial EDA tools and advanced PDKs are protected by multiple NDAs, limiting access to only a small number of companies and research institutions. To recover the skills lost during the prolonged period of talent outflow—and to cultivate a new generation of 10,000 semiconductor engineers—Japan must establish development environments based on open hardware and software that anyone can access.
Specifically, it is essential to enable trainees to experience the full chip development cycle—specification → RTL → GDS-II → fabrication → evaluation—using open-source tools and free or low-cost shuttle (MPW) services. Rebuilding the talent development pipeline and creating widely accessible design environments are critical steps in supporting the revival and long-term sustainability of Japan’s semiconductor industry.

Noritsuna Imamura｜ISHI-Kai, OpenSUSE
Noritsuna began his involvement in open-source development through the IPA Unexplored Software Creation Project and has contributed significantly to the growth of Japan’s OSS community by helping establish the Japan Java User Group and the Japan Android Group. Later, through his work in space development and the design of small satellites, he recognized the need for the “mass production and democratization of hardware.” This led him, together with Dr. Tsuchiya of The University of Shiga Prefecture, to establish ISHI-kai, an open-source semiconductor community. He is currently promoting open hardware design education for the RISC-V era through initiatives such as TinyTapeout.

17:35-17:45Video
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RISC-V Day 2025 Autumn Closing Remarks
RISC-V continues to expand its presence across the computing landscape. Compared with last year, the architecture has made further inroads in GPU host processors, AI chip host CPUs, and embedded systems. At the same time, RISC-V has not yet achieved dominance in any single application domain—an outcome that is unsurprising given that the technology has already reached a stage of broader maturity. One area where RISC-V is demonstrating particularly strong momentum is security. Leveraging its licensing flexibility and open ecosystem, RISC-V is beginning to play a central role in new secure computing architectures.

In this context, Prof. Amano’s team is advancing work on Agile-X, a cluster-based building block utilizing RISC-V, as well as the SLIMLET system. In parallel, the Japanese translation of Computer Architecture: A Quantitative Approach, 7th Edition by Hennessy and Patterson is underway, further supporting the ecosystem’s growth in Japan.

The next RISC-V Day event is scheduled for March 5, 2025.

Hideharu Amano | Senior Researcher, Institute of Industrial Science, System Design Research Center (d.lab), The University of Tokyo Advanced Design Division / Fundamental Design Division
Dr. Hideharu Amano is a Senior Researcher at the System Design Research Center (d.lab), Graduate School of Engineering, The University of Tokyo. He has long contributed to the fields of computer architecture, parallel systems, and reconfigurable computing. His recent activities include research on RISC-V–based system design and next-generation agile semiconductor development platforms. Dr. Amano continues to play a leading role in advancing innovative computing architectures in Japan.

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Presentation Title
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9:00-13:00

Hands-on Tutorial and Demo: OpenROAD and Tiny Tapeout Workflow
This hands-on tutorial uses the open-source EDA tool OpenROAD and the educational TinyTapeout platform to guide participants through the fundamental workflow from LSI design to chip fabrication. Participants will gain practical experience with design automation, physical implementation, and verification processes by performing each step interactively. Building on the SkyWater 130nm (Sky130) open process, the tutorial walks through digital logic design in Verilog, open-source EDA tools such as OpenLANE, xschem, ngspice, and KLayout, and automated GDSII generation via GitHub Actions. By completing a full tapeout flow, participants will experience how open-source tools and community-driven platforms make ASIC manufacturing accessible. The goal is to provide participants with a hands-on understanding of open-source hardware design methodologies and the educational potential of the TinyTapeout ecosystem. You can gain hands-on experience in chip design through a 3-hour practical workshop. Please bring your own PC; open-source EDA tool Docker images will be installed on-site. Windows users should pre-install WSL (Ubuntu 24.04 recommended), and Mac users should ensure the latest version of Docker is installed. After the workshop, there will be talks and exhibits on chip design projects using open-source tools. Each participant will receive a complimentary copy of “Google Semiconductor, RISC-V, and the Geopolitics of Electronics” (retail price ¥2,000, tax included). (Advance registration is necessary.)

Noritsuna Imamura, ISHI-Kai, OpenSUSE
Click for Preview Material
Noritsuna began his involvement in open-source development through the IPA Unexplored Software Creation Project and has contributed significantly to the growth of Japan’s OSS community by helping establish the Japan Java User Group and the Japan Android Group. Later, through his work in space development and the design of small satellites, he recognized the need for the “mass production and democratization of hardware.” This led him, together with Dr. Tsuchiya of The University of Shiga Prefecture, to establish ISHI-kai, an open-source semiconductor community. He is currently promoting open hardware design education for the RISC-V era through initiatives such as TinyTapeout.