Commerce and Information Policy Bureau, Ministry of Economy Technology and Industry

Andrés Lagar-Cavilla | Distinguished Engineer  | Google LLC Mountain View, California, USA

 
Moderator / Panel Leader to be confirmed | RISC-V Alliance Japan

RISC-V Working Group: Japan Embedded Systems Technology Associations (JASA)

Japan’s Semiconductor Strategy 2025 | Commerce and Information Policy Bureau, Ministry of Economy, Technology and Industry
This presentation outlines Japan’s Semiconductor Strategy 2025, an initiative led by METI to rebuild Japan’s semiconductor ecosystem and enhance its role in global supply chains. Amid rapid digital transformation and intensifying concerns over economic security, the strategy seeks to strengthen Japan’s technological base through collaboration among industry, academia, and government. Its priorities include: Reinforcing R&D and manufacturing capabilities for next-generation semiconductors and advanced packaging, Expanding digital and AI infrastructure to meet growing data and computing demands, and Cultivating talent and innovation ecosystems in both hardware and software. Rather than a single industrial policy, the initiative reflects Japan’s broader commitment to secure, sustainable, and globally connected semiconductor development—anchored in partnerships with like-minded economies and the private sector.

Caliptra and OpenTitan Tutorial  | Andrés Lagar-Cavilla | Google LLC Mountain View, California, USA
This tutorial will focus on Caliptra, an open Root of Trust (RoT) project under the Open Compute Project (OCP) led by Google and Microsoft, and supported by major semiconductor companies such as NVIDIA and AMD, as well as on OpenTitan, an independent RoT chip initiative led by Google and now being mass-produced by Nuvoton.Caliptra is designed as an SoC-embedded stack that includes firmware, provisioning, and Linux integration, whereas OpenTitan aims to provide a standalone security chip. While OpenTitan represents a transparent, discrete RoT implementation, Caliptra targets the standardization of integrated RoT solutions for cloud and datacenter systems. This session will explore both projects’ design philosophies, secure boot mechanisms, and approaches to improving trust through open-source development.

Panel Discussion | RISC-V Association Japan
This panel will reexamine the significance of the Linux-class RISC-V platform defined by RVA23. While the standardization of ISA extensions continues to advance, it is the standardization of non-ISA domains—such as I/O, memory, networking, and coherence—that will ultimately determine implementation interoperability. The session will explore the current state and challenges of platform standardization within the RISC-V ecosystem from both hardware and software perspectives.

Activities of RISC-V Working Group of JASA RISC-V Working Group  | RISC-V Working Group, Japan Embedded Systems Technology Associations (JASA)
In recent years, the JASA RISC-V Working Group, efforts have focused on promoting understanding of RISC-V and validating implementation technologies. The group first implemented a RISC-V processor on FPGA, followed by a prototype chip fabricated through the Google Shuttle program, on which functional demonstrations and software evaluations were conducted. Currently, the group is developing an original in-house RISC-V chip design, achieving successful demonstrations at each stage. This presentation will highlight these achievements and discuss future development plans.

Japan’s Semiconductor Strategy 2025 
This presentation reports on the key points of Japan’s “Semiconductor Strategy 2025,” promoted by METI. Against the backdrop of rapid digitalization and growing importance of economic security, the Japanese government positions semiconductors as “the rice of all industries” and aims to strengthen national competitiveness. Industry, academia, and government are working together under three main pillars: (1) enhancing semiconductor technology and manufacturing capabilities, (2) developing digital infrastructure, and (3) fostering the software and IT industries. The session will share the direction of ongoing policy discussions and future outlook.

Andrés Lagar-Cavilla | Distinguished Engineer  | Google LLC Mountain View, California, USA| Google LLC Mountain View, California, USA
H. Andrés Lagar-Cavilla is a Principal Engineer at Google, where he leads efforts at the intersection of open hardware security and confidential computing. Within the Open Compute Project (OCP), he serves as one of Google’s principal technical representatives, shaping the direction of the Open Compute Security Project (OCSP) and the Data Center Secure Control Module (DC-SCM) specifications. Through this work, he defines how open server architectures implement a consistent Root of Trust, secure boot, and attestation framework across hyperscale systems. At Google, Andrés drives the integration of platform-level trust mechanisms—from DC-SCM’s hardware-anchored security to higher-layer HSM services and confidential computing environments—to establish verifiable end-to-end protection for data in use. His leadership ensures that Google’s internal infrastructure and the broader OCP ecosystem advance together toward transparent, interoperable, and cryptographically verifiable security foundations. By bridging open standards and production-scale systems, Andrés continues to redefine how modern data centers achieve trust by design.

Moderator / Panel Leader TBD (to be confirmed)

Activities of RISC-V Working Group of JASA  | Japan Embedded Systems Technology Associations (JASA)
In recent years, the JASA RISC-V Working Group, efforts have focused on promoting understanding of RISC-V and validating implementation technologies. The group first implemented a RISC-V processor on FPGA, followed by a prototype chip fabricated through the Google Shuttle program, on which functional demonstrations and software evaluations were conducted. Currently, the group is developing an original in-house RISC-V chip design, achieving successful demonstrations at each stage. This presentation will highlight these achievements and discuss future development plans.