Reception

Words of Welcome

Opening: Japan’s Strategy for Digital Industry and Semiconductor Fabs (Invited Lecture)

10 Minute Reseating | Bio Break

Introduction of high-performance RISC-V and domain-specific acceleration (DSA) for data center applications (tentative title)

Satoru Yamaguchi | Ventana Micro Systems Japan (USA)

Former Apple A | M series CPU design lead explains design trade-offs in Ascalon RISC-V CPU: ARM vs. RISC-V, Vector vs. Tensor, Hardware vs. Software (tentative title)

The RISC-V architecture for the future of Generative AI and HPC

12:00-13:00

60 minute Lunch Break

Poster Session Introduction

13:20-13:50

Accelerating RISC-V HW & SW Development Using Fast Processor Models

Electrifying and Autonomizing Automobiles with RISC-V and Accelerators (tentative title)

Geir Eide | Tessent Embedded Analytics Product Manager, Siemens EDA

15 Minute Reseating | Bio Break

RISC-V solutions and custom compute recommendations for memory safety with CHERI

Video

PDF

ARC-V”: Synopsys RISC-V Processor IP Accelerating Innovation in Automotive, AIoT & Consumer Markets

Video

PDF

Combo Wireless RF RISC-V Flash MCU Platform for Office Equipment, Payment Terminals, and IoT (tentative title)

DMCO & RUMS- New value proposition Rapidus aims to offer as a leading-edge foundry

17:15-17:35

30

J

Delivering the Future of Automotive Innovation with RISC-V: RISC-V International Automotive Special Interest Group

17:40-17:50

10

J

Closing Speech

Makoto Ikeda | University of Tokyo

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Cleanups

15:00-15:20

Ventana Microsystems system description

Satoru Yamaguchi | Ventana Microsystems Japan

Recent activities of the AI chip Design Center and Post-Moore Semiconductor Technology (tentative title)

Introduction of memory safety technology “CHERI” and RISC-V implementation demo

J

Cleanups

13:00-13:20

Development of the JASA Profile of RISC-V platform

Tomohisa Kohiyama (Hitachi Industrial Equipment Systems Co., Ltd.) | Technical Headquarters Hardware Committee RISC-V Working Group Chief, Embedded Systems Technology Association (JASA)

Video

PDF

20

Understanding Open Source Silicon Correctly

Video

PDF

20

Making Open Source ASIC / LSI / IC Manufacturing Accessible and Realizing cross-Disciplinary Innovation Through Collaboration (tentative title)

20

A RISC-V/FPGA SoC in 55nm DDC CMOS

20

Introduction of Engineering of University of Sydney

Sandra Margon | Head, External Relations, Faculty of Engineering, University of Sydney

10:55-11:15

Developing Energy-Efficient and High-Performance Computer Architectures Using Domain-Specific RISC-V Processors (tentative title)

Jubee Tada | Associate Professor, Graduate School of Science and Engineering, Yamagata University

20

Linux on RISC-V — Software Ecosystem Update (tentative title)

20

Enhancing FPGA Overlay Performance with a RISC-V-Based Manycore Architecture (tentative title)

20

Introduction to Xnics 

20

TEE (Trusted Execution Environment) and CC (Confidential Computing) on RISC-V
Institute of Information Security (IISEC)

20

Part 1:  Project Open Se Cura:  System Architecture and Reference Design

 20

Part 2: Project Open Se Cura: System Components and Design Toolchain

Evaluation of RISC-V Bi-Endian and Variable Register Size Functionality Utilizing a Hypervisor

rv64ilp32: The future of 32-bit Linux

15-Minute Reseating | Bio Break

Enhancing RISC-V: Hardware Acceleration, Cryptography, and Security Solutions (tentative title)

RuyiSDK: Preparing for 1 million RISC-V software developers

E

Farewell Remark

Siemens EDA

Siemens EDA

F

 12:00 – 17:00

Verisilicon Japan

Academic Communal Demo Exhibition 

5

Communal Demo Space

6

Exploring interconnect structure and wiring optimization in FPGA-based many-core architecture

Workshop on Software, Architecture and Theory for Secure Systems

Hiroshi Ishikawa (National Institute of Informatics), Kenji Kawano (Keio U), Kenichi Korai (Kyushu Technology U), Kuniyasu Suzaki　（Institute of Information Security), Kento Aida (National Institute of Informatics),  Atsuko Takefusa (National Institute of Informatics), Keiji Kimura (Waseda U), Shinya Takamaeda (U of Tokyo), Ryota Shioya (U of Tokyo), Masahiro Goshima (National Institute of Informatics), Atsushi Igarashi (Kyoto U), Ichiro Hasuo (National Institute of Informatics), Taro Sekiyama (National Institute of Informatics)

Evaluation of Soft-processor RISC-V for Edge Computing Applications

Guillermo Montesdeoca, Victor Asanza, Rebeca Estrada, Christian Ramirez and One Person | Escuela Superior Politecnica del Litoral, Espol (FIEC & CTI) SDAS Research Group, SDAS Research Universitat Politecnica de Valencia

CV32E40P updates: customizing an open-source RISC-V core at industrial-grade; experiences and challenges

Florian Wohlrab and Pascal Gouedo, Dolphin Design OpenHW Group

Transient Execution Attacks and Countermeasures on RISC-V Implementations

Tuo Chen, Kuniyasu Suzaki (Institute of Information Security)

An Implementation of SHA3 Accelerator Using RISC-V RoCC Coprocessor On ArtyA7 100T Board

Duc-Thuan Dam, Trong-Thuc Hoang and Cong-Kha Pham | University of Electro-Communications

A Multi-purpose RISC-V Framework

Binh Kieu-Do-Nguyen, Cong-Kha Pham and Trong-Thuc Hoang | University of Electro-Communications

PDF

Live Demonstration: Linux-bootable Trusted Execution Environment (TEE) System-on-chip (SoC) with Cryptographic Accelerators

Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham | The University of Electro-Communications (UEC), Tokyo, Japan

PDF

Live Demonstration:
Rocket-core on ROHM-180nm and VexRiscv-core on SOTB-65nm

Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham | The University of Electro-Communications (UEC), Tokyo, Japan

PDF

Venue Opens 

Welcome Greeting

Explaining RISC-V in 10 minutes (what it is, background, current situation, social impact)

Free Discussion

Riuko Sugimoto | Freelance Journalist

The venue remains Open – Chat Time continues

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Withdrawal

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