Ministry Economy, Trade and Industry
SAITO Hisashi | Deputy Director, IT industry division, Commerce and Information Policy Bureau, Ministry Economy, Trade and Industry / I have been working at Japan’s semiconductor company from 2011 to 2020 and I researched semiconductor devices. In January 2021, I joined METI. Now I am working for R&D budget of semiconductor, AI, computing technology.
Tenstorrent is a next-generation computing company that builds computers for AI. Headquartered in Toronto, Canada, with U.S. offices in Austin, Texas, and Silicon Valley, and global offices in Belgrade, Tokyo, and Bangalore, Tenstorrent brings together experts in the field of computer architecture, ASIC design, advanced systems, and neural network compilers.
Jim Keller | Jim Keller, CEO of Tenstorrent and veteran hardware engineer, has had an illustrious career in tech. Formerly SVP of Intel’s Silicon Engineering, he’s also led roles at Tesla, AMD, and P.A. Semi. His achievements include designing successful silicon chips for DEC Alpha, AMD Zen family, Apple A4/A5, and Tesla’s self-driving cars.
Presentation Outline : Tessent Embedded Analytics provides comprehensive support for designers and users of RISC-V processors, with semiconductor IP and tools supporting single-core, multi-core, and heterogeneous SoC architectures. Embedded Analytics solutions include all of the run control, standards-based trace and in-field optimization features that the ecosystem requires.
Siemens offers comprehensive RISC-V solutions including DFT solution for silicon debugging and bring-up, RISC-V integrity verification solution that apply formal verification methodology, and high-level design solution rationing for shift-left in the design cycle, as well as RTOS, middleware, IP, tools, and services to enable jump-starting embedded system development.
Hiroshi Fujimatsu | Technology Solutions Sales, Field Application Engineer, Siemens| Siemens EDA
Presentation Outline : This talk will showcase Imagination Technologies’s RISC-V journey, introduce Catapult product line, give detailed insight into its first 32-bit embedded CPU, RTXM-2200 and Catapult SDK(Compiler, IDE and enhanced debugging) and finally, will also highlight Imagination Technologies’s deep engagement within RISC-V International.
We will also highlight our deep engagement within RISC-V International.
Imagination Technologies Imagination is a UK-based company that creates silicon and software IP designed to give its customers an edge in competitive global technology markets. Its GPU, CPU and AI technologies enable outstanding power, performance, and area (PPA), fast time-to-market and lower total cost of ownership. Products based on Imagination IP are used by billions of people across the globe in their smartphones, cars, homes, and workplaces.
Haruhiko Ogawa | Staff Field Application Engineer, Imagination / Haruhiko Ogawa graduated from the Tokyo Institute of Technology and has been involved in logic design in the semiconductor industry. Since 2008, he has been working at Imagination Technologies.
Presentation Outline : Green Hills Software’s products and services support a wide range of 32/64-bit RISC-V processors and offer safety and security-certified real-time operating systems, virtualization and advanced development tools to developers of production-focused systems for automotive, industrial, IoT and military/aerospace applications.
Green Hills Software GK | GHS’s products are platform-independent, functional safety-certified secure real-time operating systems and embedded development solutions that support a very wide range of hardware and software platforms.
Ryan Kojima is a graduate of the esteemed Suzuka National college of Technology in Japan, where he studied Electronic and Information Technology. In his early career he worked as a System Engineer for printing automation system design and implementation, and moved to the US while working in application design where he had a development team lead role and responsibilities in business development. After joining Green Hills Software in 2018, he has worked as an Embedded Software Consultant assisting Green Hills Software’s customers around the world, with a special focus on the Japan and Asian markets where he works closely with key regional partners including Renesas Electronics Corporation.
Presentation Outline: We present GD32VF103 series embedded RISC-V core, development tools, evaluation boards and adoption cases.
GigaDevice is a leading fabless company engaged in advanced memory technology and IC solutions. The company was founded in Silicon Valley I n 2004 and currently produces a wide range of SPI NOR Flash, SPI NAND Flash, sensors and MCUs for use in embedded, consumer, and mobile communications applications with more than 1 billion units shipped every year. In 2019, GigaDevice launched the world’s first 32-bit RISC-V based general purpose.
Ken Kageyama has been involved in the development, product planning, marketing and sales of semiconductor products such as MCUs, ASICs, IPs, dynamic reconfigurable processors and flash memories.
Lauterbach Japan Ltd. / Lauterbach has been providing debugging tools in the field of embedded software development for over 40 years, supporting more than 80 different core architectures and becoming the de facto standard for hardware-assisted debugging tools.
Takahito Kagawa, Sales Manager / Over 20 years of experience in technical support and sales of embedded software support devices such as ICE and JTAG debugging tools.
Presentation Outline: The Japan Science and Technology Agency (JST) is welcoming proposals in various advanced research fields that will nurture the next generation of research leaders and establish sustainable international partnerships.
JST (Japan Science and Technology Agency) is a national research and development Agency that plays a central role in the Science, Technology and Innovation Basic Plan* and aims to promote science and technology.
TomohiroTeraminami | Japan Science and Technology Agency / Senior Program Coordinator (Japan)
Presentation Outline : Software simulation can accelerate project schedules. While the technology has been available for over 15 years, the flexibility of RISC-V is increasing the need for software development before hardware is available. This talk highlights the use of virtual platforms for RISC-V software development, including analysis of optimizations with custom instructions.
Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas promotes open-source models for CPU architectures, cores, system IP and reference models of processors ranging simple single core bare metal platforms to full heterogeneous multicore systems booting SMP Linux.
eSOL Trinity Co., Ltd. was established in 2015 as a wholly owned subsidiary of eSOL Co., Ltd. Its three core businesses are Tools, Solutions, and Education, with a focus on RISC-V, ISO 26262, and Cyber Security.
Yukiharu Sato / Senior Product Sales, Sales division, eSOL TRINITY Co., Ltd. | Joined ERG Co., Ltd. (now eSOL Co., Ltd.) in 1987. Worked as an embedded software engineer, then moved from a management position in software development to the sales department. From this year, moved to the sales department of eSOL TRINITY Co., Ltd. (a wholly owned subsidiary of eSOL) .
Presentation Outline : Since our last talk in 2021, Espressif has been working on more chips incorporating Risc-V processors. This talk will provide an overview as well as illustrate some design choices.
Espressif Systems is a prominent multinational fabless semiconductor company that was established in 2008. It’s renowned for its pioneering Wi-Fi-and-Bluetooth and low-power Internet of Things microchips and solutions. The company is committed to providing secure, reliable, and energy-efficient solutions to its customers.
Jeroen Domburg is a Senior Software and Technical Marketing Manager at Espressif Systems. With more than 20 years of embedded experience, he is involved with both the software as well as the hardware design process of Espressifs SoCs.
Presentation Outline : For a long time, Moore’s law was supported by theories such as Dennard scaling and Amdahl’s law and had overcome many hardships. But with the end of those theories, Moore’s law is barely alive. One way to keep it alive is through Custom Compute for specific domains (applications). Instead of off-the-shelf processor IP, which has been utilized for approximately 20 years, you now have access to custom processors optimized for each application. RISC-V is the perfect foundation for Custom Compute.
Codasip | Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream.
Takaaki Akashi / Japan Country Manager, Codasip / Successfully evangelized Verilog (IEEE std. 1364-1995) at Cadence at the start of the 1990s, and SystemVerilog (IEEE std. 1800-2005) and VMM, which is the archetype of UVM at Synopsys in the early 2000s, as a member of the JEITA (formerly EIAJ) standardization committee. Involved in semiconductor design in Japan for more than 25 years.
Presentation Outline : NSITEXE has developed a processor-centric product under the name of Akaria, which provides a RISC-V core as Akaria’s Standard Processor and combines it with an expansion unit to form a Domain Specific Accelerator. In this presentation, we will introduce some application examples of Akaria utilizing RISC-V.
NSITEXE is an IP vendor developing advanced processors, established in 2017 as a spin-off from Denso Corporation. We develop RISC-V based processor IP for functional safety. Our highly efficient, high-quality semiconductor IP supports a wide range of applications and contributes to the evolution of next-generation semiconductor technology.
Tomoaki Katano | NSITEXE,Inc. (Japan) / After joining a consumer electronics manufacturer in 1999 and being assigned to the semiconductor division, he was in charge of EDA technology development, virtual platform launch, system verification management, new business development, and various other functions in the semiconductor business, He started his activities there with the establishment of the company in September 2017. Currently, as Technical Marketing Manager, he is responsible for the company’s technical planning, product strategy, and promotion.
Presentation Outline : We believe that the key to utilizing RISC-V is the ecosystem. Is it sufficient to use only open source compilers to utilize open source ISAs? IAR’s compiler is one option.
IAR provides world-leading software and services for embedded development, enabling companies worldwide to create secure and innovative products for today and tomorrow. Since 1983, IAR’s solutions have ensured quality, security, reliability, and efficiency in developing over one million embedded applications for companies across industries such as industrial automation, IoT, automotive and medical.
Hiroki Akaboshi / He has been involved in in-vehicle software development for more than 20 years. Has extensive experience in model-based development, HILS construction, meter/HV/engine ECU development support, coding rule support, software behavior analysis, etc. At IAR Systems, provides technical proposals and supports to customers. Also wrote books on Embedded Workbench and model-based development.
Presentation Outline : 2 years ago Google started an experiment to boostrap an open source silicon ecosystem: after releasing 2 open source PDKs and organizing 9 shuttles, we present a retrospective of short retrospective of the challenges we met and what we learned from them.
Google believes that open source is good for everyone. By being open and freely available, it enables and encourages collaboration and the development of technology.
Johan Euphrosine (proppy) is a Developer Relations Engineer working from Google Japan, Johan started at Google 12 years ago and has been focusing on improving the developer experience of a variety Google Developer products. Johan joined the Hardware Toolchains team last year and has been contributing to growing the ecosystem around open source silicon.
Presentation Outline : Our team supports all things related to university research engagements at Google, and our work is geared towards supporting research in fields related to computer science. Today I’ll share the reasons we care about having great research relationships with universities and how we support the academic ecosystem globally.
Google believes that open source is good for everyone. By being open and freely available, it enables and encourages collaboration and the development of technology.
Ryo Shigeta joined Google Japan in Feb 2020 as a Universiry Relations Program Manager and supports collaborations between Google and Japanese universities. I received PhD in 2018 and worked as a researcher for agricultural IoT projects. Also worked closely with deep-tech start-ups (SenSprout, Tenchijin).
Greg Favor | Co-Founder and Chief Technology Officer / Ventana Micro Systems / Greg has been architecting and designing microprocessors for 38 years, both at startups and large companies, and across many architectures including x86, PowerPC, ARMv8, and now RISC-V. Most recently this includes being co-founder and CTO of Ventana Micro Systems, which is developing high performance RISC-V processors. Greg is also currently Chair of the RISC-V Privileged Architecture ISA Committee, and is actively involved with a number of RISC-V Task Groups.
Travis Lanier | Vice President of Marketing, Ventana Micro Systems / Travis Lanier is the Vice President of Marketing at Ventana with over 27 years of experience in CPU development. He began his career at AMD, where worked on the K5, K6, and Athlon processors. He then spent over a decade at Arm, where he worked in both engineering and product management on many key technologies, including BIG.little, NEON, and Arm’s early data center efforts with Cortex-A15 and later their first 64-bit processors. In 2011 he joined Qualcomm, where he managed their technology roadmap for a broad portfolio of processor technologies, including CPU, DSP, AI, security, and compilers across their entire portfolio of products, including mobile, automotive, and data center. Travis earned an MS in computer engineering from the University of Texas at Austin, and BS in electrical engineering from Louisiana State University.
Presentation Outline : Introducing the Andes RISC-V core that enables the future of IoT. introducing a vector processor suitable for realizing AI processing on edge device from a compact and low power controller, and a high end core also Andes is supporting automotive functional safety products.
Andes Technology Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream.
Triton corporation where is distributor of Andes Technology core in Japan.
Hiroaki Sato is a senior advisor for Triton corporation where is distributor of Andes Technology core in Japan. He has CPU promotion background such advanced technology area and IoT device area. Especially, he has backend experience such CPU implement based on advanced process node.
Tenstorrent is a next-generation computing company that builds computers for AI. Headquartered in Toronto, Canada, with U.S. offices in Austin, Texas, and Silicon Valley, and global offices in Belgrade, Tokyo, and Bangalore, Tenstorrent brings together experts in the field of computer architecture, ASIC design, advanced systems, and neural network compilers.
David Bennett is CCO of Tenstorrent, has 15+ years of experience in tech with executive leadership positions in critical global regions. He previously served as CEO of NECPC, President of Lenovo Japan, and VP at Lenovo Group as well as AMD’s Corporate VP and GM of OEM Accounts Worldwide, and VP for Asia Pacific and Japan. He is also visiting lecturer at Yamagata University and a board member of Sanrio Company Ltd.
Omar Hassen | Senior Vice President Of Business Development, Ventana Micro Systems / Omar Hassen has worked in the technology industry since 1994. Omar started their career as an Engineer at SMC in 1994. In 1996, they Co-Founded Entridia Corporation. In 2002, they became a Product Line Manager at Broadcom. In 2005, they were a Sr. Director of Business Development at Marvell. In 2008, they were an Executive Director at International Rectifier. In 2012, they were a General Manager at Red Swan Consulting. In 2014, they became a Vice President of Product Management at AppliedMicro. Most recently, they have been a Senior Vice President of Business Development at Ventana Micro Systems since 2019. Omar Hassen has an MBA from the University of Southern California – Marshall School of Business, where they studied Business Administration, Management and Operations. Omar also holds a Bachelor of Science in Computer Engineering from California State University, Long Beach.
RISC-V International
Mark Himelstein | CTO, RISC-V International / Before RISC-V international Mark Himelstein was the President of Heavenstone, Inc. which concentrated on Strategic, Management, and Technology Consulting providing hardware and software product architecture, analysis, mentoring and interim management. Previously, Mark started Graphite Systems, Inc (acquired by EMC) where he was the VP of Engineering and CTO developing large Analytics Appliances using highly integrated FLASH memory. Prior to Graphite, Mark held positions as the CTO of Quantum Corp, Vice President of Solaris development engineering at Sun Microsystems and other technical management roles at Apple, Infoblox, and MIPS.Mark has a bachelors degree in Computer Science and Math from Wilkes University in Pennsylvania and a masters degree in Computer Science from University of California Davis/Livermore. In addition to publishing numerous technical papers and holding many patents, he is the author of the book “100 Questions to Ask Your Software Organization”.
RISC-V Alliance Japan was incorporated as a non-profit organization in Japan. The purpose is to proliferate RISC-V, open silicon technology enabling RISC-V, and system technology enabled by RISC-V to Japan and neighboring countries. Strongly motivated to ally with RISC-V organizations worldwide.
Shumpei Kawasaki co-founded SH Consulting in 2013. He specialized in the field of security for RISC-V FPGAs / SoCs. In 1990s, he co-developed CPUs and chipsets for Sega Saturn and Dreamcast video games. ARM adopted his “16-bit fixed-length instruction” invention for their monumentally successful “ARM7TDMI” and “ARM9TDMI.” In 2000s Shumpei led a development of a minimal operating system for Root of Trust chips used in network routers, 2-5G mobile handsets, and secure tokens in US.
Event Space Special Presentation Venue
Presentation
Event Space Special Presentation Venue
RISC-V Open Source Silicon Ecosystem and Advanced Research
Hideharu Amano: He will introduce “RISC-V Open Source Silicon Ecosystem and Advanced Research” (Poster Session).
Keio University Faculty of Science and Technology, Department of Information and Computer Science, Amano laboratory is focused on new computer techniques for the post-Moore era. Research includes FPGA clusters, one-chip multiprocessors, dynamically reconfigurable computers, and novel interconnection networks. Real prototype systems with original LSI chips are developed to demonstrate research results.
Hideharu Amano is a professor of Department of information and computer science, Keio University. He is now developing a chip with embedded FPGA, switch and RISC-V. He received his Ph.D. in 1986 from Keio University. He was a visiting assistant professor at Stanford University from 1989-1990. Now, he is a professor at the Department of Information and Computer Science, Keio University. Hideharu Amano started research on computer architecture under the professor Hideo Aiso, Department of Electrical Engineering, and shared memory, cache, switch chip, multiprocessor, reconfigurable system, massively parallel system, router chip, multi-context device, power saving Reconfigurable accelerator, ultra-low power processor, consistent architecture research. It is known for its approach to developing and evaluating real systems to demonstrate ideas. In addition to translating Hennessy Patterson’s “quantitative approach”, he has held numerous academic committee positions and positions.
Presentation Outline : Under a strong radiation environment, processors must have high-radiation tolerance. Currently available processors are always weak for radiation and are easily broken by radiation for a short period. Therefore, we have been developing a triple-modular-redundant processor to increase the radiation tolerance. We present one design example for an Arithmetic Logic Unit (ALU) and a register file.
The Watanabe Laboratory, faculty of engineering, Okayama University, conducts research on the integration of advanced optical technologies such as holographic memory and lasers with integrated circuits (VLSI). We are working on next-generation optoelectronic FPGAs that significantly exceed the performance of existing reconfigurable devices(FPGAs).
Masato Isobe | Faculty of Engineering, Okayama University, student / Masato Isobe is 4th grade student at Okayama University, Faculty of Engineering, Department of Information Technology. He is currently working on research and development of RISC-V processors to enhance radiation resistance.
Presentation Outline : We realize an FPGA-based quantum simulator working on Qulacs, a quantum computer simulator. The proposed design consists of two distinct parts, FPGA platform Trefoil design through the tool LiteX, an open-source framework for building digital systems on FPGA, and the quantum gate design using High-level Synthesis combined with Hardware Description Language.
Keio’s SQAI group aims to create new AI technology, including quantum machine learning, quantum simulation, and measurement in quantum mechanics. As one of the projects in SQAI, quantum simulation, we attempt to realize a quantum simulation platform that enables everyone to get an approach to quantum behaviors without the restrictions of high-spec hardware.
Kaijie Wei received M.Eng. degree in 2020 and Dr.Eng. degree in 2023 from Keio University. He is currently a Project Assistant Professor in the Department of Information and Computer Science, at Keio University. His research interests include deep learning and image processing accelerators and reconfigurable architectures.
Presentation Outline : In this poster session, we’d like to introduce the Arch Linux RISC-V port which is currently one of the most completed ports among all architecture ports of Arch Linux. With libreoffice, chromium, firefox, box64 and other necessary softwares ported and packaged, users can have a feature-rich experience on RISC-V platforms. We’d also like to mention some important works we’ve contributed to the open source community.
PLCT is committed to becoming a leader in the field of compilation technology, promoting technological innovation in open source toolchains and runtime systems, and possessing the technical and managerial capabilities to lead the development and maintenance of the latest infrastructure.
Ruizhe Pan is currently the Chair Intern at the PLCT Arch Linux RISC-V team. He is majoring Computer Science at Zhejiang University. Arranged by felixonmars, the PLCT Arch Linux RISC-V team is devoted to make Arch Linux and its packages accessible for RISC-V.
Presentation Outline : We investigate and study the current status of Quantum Computing, especially the performance of the popular gate model quantum processors. We evaluate their programmability on different cloud platforms, explore their usability with practical quantum algorithms, and test their noisy output fidelity.
The Kondo Lab focuses on domain-specific architectures which are optimized for specific applications such as graph processing and robot intelligence, and computer systems that combine the benefits of classical computing and new computing paradigms such as AI/ML, neuromorphic computing, and quantum computing.
Yikai Mao received B.S. in Computer Engineering from the Univerisity of Florida in 2018, and M.S. in Electrical & Computer Engineering from the University of California, Davis in 2021. He is currently a Ph.D. student at Keio University researching Quantum Computing and Computer Architecture, advised by Dr. Masaaki Kondo.
Presentation Outline : SoCs with mixed processor and eFPGA IPs have been studied for the recent advanced IoT endpoints. In this laboratory, we have developed “SLMLET,” a SoC with a RISC-V processor core and eFPGA, and evaluated the power and I/F of the SLMLET chip.
YANAI Yosuke | Keio University Graduate School of Science and Technology, Amano-lab
Presentation Outline : A System-on-a-Chip (SoC) with reconfigurable hardware is required to efficiently process specific workloads, while also providing low power consumption, low latency, and high throughput. SLMLET is an SoC composed of a RISC-V core and SLM reconfigurable logic that has been developed in recent years. In evaluating the SLMLET chip, which was taped out last year, we developed test environments and software development kits.
Takuya Kojima｜The University of Tokyo, Assistant professor/ Takuya Kojima received his B.E., M.E., and Ph.D. degrees from Keio University, Japan, in 2017, 2019, and 2021, respectively. Since 2021, he has been an assistant professor at The University of Tokyo, Japan. He is currently a JST PRESTO researcher as a concurrent post. His research interests include optimization methods, especially for reconfigurable devices, and heterogeneous computing with 3-D stacked LSI. He is a member of IEEE and IEICE.
Presentation Outline : Evaluation boards for side-channel analysis research are currently not updated, causing various difficulties. To solve this problem, we propose a next-generation side-channel analysis evaluation board, SHAMIKO. SHAMIKO has the latest FPGAs, supports the latest EDA, and is completely open source, providing continuous design updates and high accessibility.
SHAMIKO Project is a group of researchers who are challenging to develop SHAMIKO(Side-cHannel Attack experiMents and Implements Kindly bOard), a next-generation FPGA board that will replace the SASEBO- and SAKURA-series FPGA boards.SHAMIKO will be provided with long-term support and open source.
Questions, participation and sponsorship are welcome!
Presenter : Ryotaro Ohara | Received his Foundation degree from Tokyo Metropolitan College of Industrial Technology in 2016 and, B.Eng.in Environmental and Life Science from Toyohashi University, and Master of Science, Technology in 2018, and Innovation from Kobe University, Hyogo, Japan, respectively, in 2021. His current research is a non-contact environment monitoring by Ultrasonic
Co-author : Haruka Hirata | First year of a Ph.D program at The University of Electro-Communications.
Presentation Outline：Low power is one of the essential requirements for the Internet of Things (IoT). This study shows the trade-offs of two different RISC-V microprocessor architectures named SERV for the same application, with evaluation criteria including minimum power consumption and area overhead, precisely the effect of the number of registers in the Register File.
The University of Electro-Communications (電気通信大学) is a national university in the city of Chōfu, Tokyo, Japan. It specialises in the disciplines of computer science, the physical sciences, engineering and technology. It was founded in 1918 as the Technical Institute for Wireless-Communications.
Khai-Duy Nguyen received the B.Sc. degree in electronics from the University of Science and Technology, The University of Danang, Danang, Vietnam. He is currently a Master student The University of Electro-Communications (UEC), Tokyo, Japan.
Presentation Outline：This poster presents an efficient strategy for attacking the cryptographic RISC-V SoC using the well-known Correlation Power Analysis (CPA) technique. In CPA attacks, the attackers use a power model to predict the power consumption of the device under test. In each model, the effectiveness of an attack depends on the transition factor φ, which is a ratio related to different characteristics of the device’s power consumption. This proposal introduces a solution to estimate the quantity of leakage information by determining the relationship between the SNR and φ. The experimental results show that applying the Switching Distance model brings the highest performance.
The University of Electro-Communications (UEC) is a national university in the city of Chofu, Tokyo, Japan. It specializes in the disciplines of computer science, the physical sciences, engineering, and technology. It was founded in 1918 as the Technical Institute for Wireless-Communications.
Tran Thai Ha (チャン・タイ・ハ) received the B.Sc. degree in electrical and electronic engineering and the M.S. degree in electronic engineering from Le Quy Don Technical University, Hanoi, Vietnam, in 2012 and 2018, respectively. He is currently pursuing the Ph.D. degree in information and network engineering at the University of Electro-Communications (UEC), Tokyo, Japan
Presentation Outline： 本研究では、新しいデータ転送方式としてベクトルレジスタ共有機構を提案し、実装した。評価の結果，RV64GCに比べてベクトルレジスタ共有機構の方がアクセラレータに十分なデータを供給できることが明らかとなった。後の展望として、比較対象としてDMAの実装と比較評価のためのアプリケーションを拡充させていく。
Tokyo University of Agriculture and Technology
Michiya Kato | Department of Electrical Engineering and Computer Science, Graduate School of Engineering, Tokyo University of Agriculture and Technology
University of Tsukuba
Masaru Nishimura | Graduate school of Science and Technology, University of Tsukuba / Master’s student / He is a master student of computer science at the University of Tsukuba from 2022. His research interest is many-core processor architecture.
Event Space Special Presentation Venue
Presentation
Efabless corporation is an open innovation, hardware creation platform for “smart” products. Our community delivers the customized integrated electronics required for semiconductor and hardware system innovators to turn their product visions into a marketable reality. Our mission is to democratize the process of electronics product creation, making it accessible to all who want to participate.
Mohamed Kassem is the CTO and Co-Founder of efabless.com, the first semiconductor company applying open community innovation to all aspects of product development. Prior to launching efabless in 2014, Mohamed held several technical and global leadership positions within Texas Instruments’ Wireless Business Unit. He joined TI in 2000 at the beginning of the digital telephony revolution fueled by the unprecedented integration of major phone functions on a single SoC. He led the first development of 45nm, 28nm analog & mixed-signal IP functions for wireless applications processors.
Mohamed holds a Masters degree in Electrical Engineering from the University of Waterloo, Ontario, Canada.
University of Electro-Communications, Information Security Program
Kazuhide Uchiyama is a fourth-year undergraduate student at the University of Electro-Communications. He majors in information security and has a keen intellectual curiosity. Kazuhide started designing self-made CPUs on FPGA and has since been involved in building a community for self-made CPUs with his friend Yuki. They also create Japanese documentation for tools used in open-source silicon.
University of Tsukuba, Department of Physics, Theoretical Astrophysics Group
Yuki Azuma | University of Tsukuba, Department of Physics, Theoretical Astrophysics Group / Yuki Azuma is a fourth-year student at the University of Tsukuba, Department of Physics. He enjoys building his own CPUs and operating systems to understand how they work. Yuki has a keen interest in understanding the underlying principles of how things operate. A year and a half ago, he and his friend Kazuhide learned about the OpenMPW program. They tried their first attempt at digital LSI fabrication together.
University of Michigan (EECS) | Michigan Engineering, Electrical Engineering and Computer Science Department (EECS)
Mehdi Saligane | University of Michigan / Michigan Engineering, Electrical Engineering and Computer Science Department (EECS) / Assistant Research Scientist, Intermittent Lecturer at University of Michigan / Mehdi Saligane is a Research Scientist in the Department of Electrical Engineering and Computer Science at the University of Michigan. He received his M.Sc. and Ph.D. degrees in electrical and computer engineering from the University of Grenoble and Aix-Marseille in 2011 and 2016, respectively. He worked at STMicroelectronics, in France, as a Research Engineer from 2010 to 2015, and after completing his Ph.D., he joined the Michigan Integrated Circuits Lab at the University of Michigan. Dr. Saligane’s current research interests are in low-power and energy-efficient IC design with a recent focus on open-source EDA and analog and mixed-signal IC design automation. He currently serves as chair of the Analog Working Group and, as a member of the Technical Steering Committee at CHIPS Alliance, and as a technical member of SSCS’ open source ecosystem.
The Japan Embedded Systems Technology Association (JASA) conducts research, promotion, dissemination, and enlightenment of applied technologies in embedded system technology, including embedded software. An organization that aims to contribute to the sound development of Japanese industry and the improvement of people’s lives by improving the sophistication and efficiency of Japan. The RISC-V WG belongs to the Hardware Committee of the Technical Headquarters and aims to popularize RISC-V in embedded systems.
Tomohisa Kohiyama | JASA RISC-V WG, Chief / He is a master’s degree graduate of the Graduate School of Science and Engineering, Tokyo University of Science. P.E.Jp (Electrical and Electronics, Information Engineering, Engineering Management). He joined Hitachi, Ltd. Microelectronics Products Development Laboratory in 1984. After working as the research manager of the Systems Development Laboratory, launching a company-wide thin client system as a Corporate Senior Staff at the head office. He engaged in the development of new wireless-related businesses. Currently, he is working on the DX conversion of the site as the Chief Engineer of Hitachi Industrial Equipment Systems Co., Ltd. He is the chief of JASA RISC-V WG. IEEE WCP, IPSJ CITP. Chip collector such as CPU and peripherals.
Red Hat is the world’s leading provider of open source solutions. An open development model connects Red Hat associates to open source communities. Red Hat builds and supports open source products from open source projects, participates in the projects and communities our products depend on, often in leadership roles.
Wei Fu is a opensource software developer with Embedded/Enterprise/Vehicle experience on Linux kernel/driver, BSP, system porting, CI-loop, Koji system and Distros. Also have rich experience on Firmware (U-boot/arm-TF/UEFI/ACPI/GRUB).
Currently studying Linux distro,like Fedora/RHEL/CentOS/RHIVOS, and focusing on promoting RISC-V to Fedora Primary Architectures and Automotive.
Presentation Outline : RISC-V workstations and servers that are sufficient to support daily office and development are also likely to become popular this year. The characteristics of RISC-V modularization and customization provide new challenges for RISC-V software development. RuyiSDK is a developer toolbox for RISC-V developers developed by the ISCAS. It uses a package system to maintain the software environment required by different RISC-V devices.
The Institute of Software, Chinese Academy of Sciences (ISCAS) is a research base that focuses on the research and development of theories of computer science and leading edge technologies of software. ISCAS was founded on March 1st, 1985.
Wei Wu | Director of Programming Language and Compiler Technology Lab, Institute of Software at the Chinese Academy of Sciences (China)
