9:00-
9:20

Attendees can enter 2nd basement floor and hall. Reception staffs hands out  name tags.

Staff sets up recording equipment, audio, and video systems, exhibition booths.

Program Summary

TBD

Title: Beyond Innovation: RISC-V’s Path to Mass Adoption with Mature IP

Abstract: In the AI ​​hardware market, Tenstorrent is expanding its team and shipping products by targeting development engineers and customers in the early phase of development by providing a low-cost RISC-V-based development system and an open source AI compiler stack. The company recently completed a $693 million Series D round of funding and was selected as one of the top 10 companies in the AI ​​industry. By avoiding expensive components such as high-bandwidth memory and adopting a tensor processor architecture, the company reduces the need for memory bandwidth and achieves cost performance. The company has already secured $150 million in revenue and is aiming for organic growth by focusing on small customers seeking differentiated technology. CEO Jim Keller points out that AI has the potential to significantly transform computing technology over the next 10 years. He says that the collaborative work of hardware, software, and open source will play an important role. He believes that the key to success is to create outstanding products that are centered on use cases, like Steve Jobs. Amid the tense US-China relationship, the company is showing its willingness to respond flexibly to geopolitical changes while adhering to trade regulation rules. (The title and abstract were prepared by the organizer and will be changed as soon as the abstract is prepared by the presenter.)

10:05–
10:40

Title: RISC-V Leadership in the AI Compute Era

Abstract: SiFive’s momentum continues, and the company has recently added to its broad portfolio from embedded solutions to advanced scalar and vector high performance processors. We will introduce our latest products and discuss how our roadmap is driving customers’ rapid innovations in areas like AI, data centers, automotive and the Internet of Things.

Title: Autonomous platforms driven by MIPS multi-threaded, safety-capable, efficient RISC-V compute solutions

Abstract: The drive for generative AI to evolve into physical automotive and industrial applications is pushing software-defined platforms toward zonal architectures. New compute subsystems that excel at fast data processing and precise real-time control with low latency and high efficiency are needed to address the challenges of electrification, autonomous vehicles, and industrial automation. This presentation will describe how safety-capable processor cores with multi-threading, deterministic access, RISC-V profile compatibility, and application-focused performance enhancements for data movement and memory operations are the leading choice to power the next generation of industrial robots, autonomous platforms, and electrified vehicles.

11:05–
11:15

10
min

Break time

11:15-11:40

20 min

Title: Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications 

Abstract: This presentation will illustrate the challenges and solutions of data–transport architectures for artificial intelligence/machine learning (AI/ML) in the context of embedded vision architectures and discuss implementation aspects for Networks–on–Chips (NoCs) for RISC–V–based System–on–Chips (SoCs). AI/ML and Embedded Vision architectures present unique challenges in data transport architectures to procure all relevant data from off–chip DRAMs and efficiently store and transport them in caches to allow efficient computing on SoCs and systems of chiplets. These challenges directly translate into specific requirements for NoC implementation, impacting performance, power consumption, and cost, efficiently addressing the challenges posed by what the industry calls the “memory wall” – the much faster improvement of processor vs. DRAM memory access speed. In addition, for the automotive and industrial application domains, special considerations regarding safety and resilience need to be considered to allow for ISO26262 and related certifications.

Arteris, Inc. is a technology company headquartered at Campbell, California. The company specializes in the development of network-on-chip (NoC) interconnect IP and system-on-chip (SoC) integrated automation software that are used in a variety of devices, particularly in automotive electronics, artificial intelligence/machine learning, and consumer markets. Their flagship product, FlexNoC, has been integrated into over 3 billion devices as of 2022. Additionally, Arteris offers products like Ncore, a cache-coherent interconnect IP, and CodaCache, a last-level cache IP.

(Title and abstract will be prepared by the organizer and will be changed as soon as the presenter’s abstract is ready.)

Michal Siwinski, Guillaume Boillet and John Min | Arteris (USA)

11:40-12:15

Title: Synopsys ARC-V Processor IP: The ARC-V processor IP is based on the RISC-V ISA

Abstract: The ARC-V processor family includes the ARC-V RMX, which is optimized for control and signal processing with ultra-low power consumption for embedded applications, the ARC-V RHX, a 32-bit real-time multicore processor with coherent hardware accelerators and virtualization support, and the ARC-V RPX for 64-bit SoC host applications. The RPX family includes L3 cache and a RISC-V compliant MMU to support rich OS such as Linux. Synopsys’ ARC-V FS processors are ISO 26262 (functional safety standard) ASIL-D level and are developed under an ISO 9001 certified quality management system. These processors have integrated hardware safety features to detect system errors and ensure safety. They are also ISO 21434 (automotive cybersecurity standard) compliant, allowing customers to expedite the chip certification process. Synopsys’ MetaWare Development Toolkit is provided to assist in program development, debugging, and optimization. In addition, ARC-V licensees can shorten their development schedules and bring products to market faster by leveraging tools and software from Synopsys’ ARC Access partners and the growing RISC-V ecosystem. (Title and abstract will be prepared by the organizer and will be changed as soon as the presenter’s abstract is ready.)

Speakers to be announced at a later date | Synopsys (USA)

12:15-12:30

Introduction of Poster Session Presenters: Participants in the poster session will be awarded prizes. Presenters will be asked to take to the stage in the hall.

Hironori Nakajo | Professor, Department of Intelligent Information Systems Engineering, Tokyo University of Agriculture and Technology (Japan)

13:00-15:00

Poster presentation takes place at the south foyer of Ito Hall, B2. Please refer to the floor plan maps and look for poster panel locations P1 through P10.

Poster Presenters

12:30-13:30

60 min

{Lunchtime}: RISC-V Lunch Networking Session

Staff will provide a simple lunch, courtesy of Ventana Microsystems, and drink to attendees. If staff does not reach you, please collect your lunch pack at the reception.

13:30-13:55

Title: Ventana Micro’s RISC-V Revolution: The Evolution and Market Expansion of Veyron V2

Abstract:  Ventana Micro has introduced Veyron V2, a high-performance RISC-V architecture, delivering industry-leading data center performance comparable to x86 and ARM. Key Features of Veyron V2:
①15-wide out-of-order execution pipeline
4nm process technology, operating at up to 3.6GHz; ②512-bit vector unit & AI matrix extensions; ③Scalability of up to 32 cores per cluster. Ventana has built a comprehensive ecosystem integrating chiplet technology and AI acceleration, driving adoption across data centers, automotive applications, and intelligent edge computing. With major customers incorporating the architecture into their designs, RISC-V is showing signs of transitioning into a mainstream computing architecture. Mass production of Veyron V2 is reportedly scheduled to begin in 2025, with adoption by hyperscalers and HPC customers in the US, Europe, and Asia. Ventana’s advancements mark a significant milestone in shaping the future of RISC-V technology. (The title and abstract have been provided by the organizers and will be updated once the presenter’s abstract is available.)

Satoru Yamaguchi | Ventana Microsystems (USA)

13:55-14:30

Leverage RISC-V to Win Your Success

Abstract: RISC-V’ s new, no burden characteristic makes it special; it is invisible, and it encourages innovation. It may help you and your team to achieve success through innovation. Andes provides RISC-V cores IP to help you to gain control in using RISC-V cores in building System On Chip (SoC) designs. In this presentation, Andes new RISC-V CPU IP products will be reported, roadmap plan will also revealed. This will include Out of Order RISC-V processors, RISC-V Vector processors and ISO-26262 automotive grade RISC-V processors. AI accelerator solutions will be introduced, and Andes Custom Extension electronic design automation tools will be reported as well.

Frankwell Jyh-Ming Lin | CEO and Chairman, Andes Technology (Taiwan)

14:30-14:55

Title: Advanced MCU MD6605 for power electronics control, utilizing a RISC-V CPU core, 22nm ultra-low leakage process, and ReRAM non-volatile memory technology

Abstract: Sanken Electric is a semiconductor manufacturer whose main products are power electronics control devices. Recently, Sanken had developed the MD6605, an MCU (Microcontroller Unit) for power electronics control, which utilizes a RISC-V CPU core, 22nm ultra-low leakage process, and ReRAM non-volatile memory technology for advanced power control systems.
    In addition to the RISC-V CPU core, the MD6605 employs a heterogeneous multi-core structure with a DSP (Digital Signal Processor) for digital filter processing and an EPU (Event Processing Unit) capable of high-speed task switching, achieving high efficiency and high functionality in power control systems.
    For the manufacturing of the MD6605, the 22nm ultra-low leakage process technology is used, and ReRAM (Resistive RAM) is adopted for non-volatile memory. Due to the simple structure of ReRAM, it is optimal for fine processes and improves user-friendliness by eliminating the need for block erase which
was necessary with flash memory.
    Using the MD6605, Sanken Electric plans to actively expand its product range for various power electronics control systems.

Takanaga Yamazaki | Sanken Electric, Senior Meister, Power Device Development Division, Technology Development Headquarters (Japan)

14:55-15:20

{Intermission} Demo Booths are Open

15:30-16:10

The Future of RISC-V Development Paved by Kubuds: Cross Toolchain and Optimization Technology

Abstract: Kubuds provides comprehensive software toolchains and full-stack solutions for embedded systems and PCs to support the development of the RISC-V ecosystem. The company’s strengths lie in the creation of highly efficient development environments using the latest cross-compilation tools (GCC, LLVM), in addition to open source real-time operating systems (RTOS) and optimization for Linux. In providing cross-compilation toolchains, the company has established an environment where developers can seamlessly build and run applications across different platforms, and it can be widely applied from embedded systems to PCs. In addition, the company is also focusing on the development of debugging environments, providing advanced debugging functions using tools such as GDB and OpenOCD to improve development productivity. In terms of support for integrated development environments (IDEs), the company has achieved smooth integration into mainstream IDEs such as VS Code and Eclipse, and has established an environment where developers can develop and optimize RISC-V-based applications while maintaining their existing workflow. This makes it possible to accommodate a wide range of developers, from beginners to experienced engineers. Performance optimization for RISC-V-based embedded devices provides tuning for specific applications and designs that emphasize power efficiency, and we are working to develop advanced development environments for IoT devices and industrial equipment. (The title and abstract will be created by the organizer and will be changed as soon as the abstract is prepared by the presenter.)

Presenter to be announced later | Shanghai Kubuds Technology Co., Ltd.

Poster session review and award winners announcement: Participants in the poster session will be awarded. Prize winners will be selected and awarded for their excellent presentations.

Hironori Nakajo | Professor, Department of Intelligent Information Systems Engineering, Tokyo University of Agriculture and Technology (Japan)

16:20-16:50

Japan’s Semiconductor and Digital Industrial Strategy: Semiconductors are a key technology for Japan’s future in terms of digital transformation (DX) and green transformation (GX). METI has responded to domestic and international technological innovations and market trends based on the Semiconductor and Digital Industrial Strategy formulated in 2021. In June 2023, METI revised the strategy to focus on strengthening the semiconductor supply chain, expanding the domestic manufacturing base, and developing human resources amid growing geopolitical risks and the importance of economic security. Further revisions will be made in December 2024, including promoting additional investment in next-generation process technologies and building new global partnerships. This presentation will detail the latest strategic revisions and the initiatives recently announced by METI. Specifically, specific semiconductor-related strategies will be discussed, including strengthening domestic and international cooperation and supporting small and medium-sized enterprises in improving their competitiveness. METI will also introduce policies for strengthening research and development through industry-academia collaboration and human resource development through the expansion of specialized education programs. We will share the role Japan should play in the global semiconductor industry and specific initiatives to promote innovation. We will present a path to mitigate economic security risks and achieve sustainable industrial growth. (The title and abstract will be prepared by the organizers and will be changed once the abstract is prepared by the presenter.)

Hisashi Saito | Deputy Director, IT industry division, Commerce and Information Policy Bureau, Ministry Economy, Trade and Industry

16:50-17:00

Next-generation semiconductor engineer training program in collaboration with d.lab at the University of Tokyo and Tenstorrent: The System Design Research Center (d.lab) at the University of Tokyo is collaborating with Tenstorrent, a US AI chip startup, to train semiconductor engineers. As part of the Technology Research Association’s Leading Semiconductor Technology Center (LSTC), this initiative will see Japanese engineers dispatched to Tenstorrent in 2024 to work on designing semiconductors for AI. The expected dispatch period is one to two years, and after returning to Japan, they are expected to play an active role in telecommunications and automotive-related companies and research institutes. The program aims to train 200 engineers over five years. d.lab will lead the University of Tokyo’s inter-departmental education program “Semiconductor Education Program (SPIRIT)” from April 2024, and is working to produce human resources with a wide range of semiconductor knowledge. This aims to train human resources who can take on design using advanced devices. (Title and abstract will be prepared by the organizer and will be changed as soon as the presenter’s abstract is ready.)

Makoto Ikeda | The University of Tokyo (Japan)

17:00-17:10

10

min

Introduction to Tenstorrent’s Advanced Digital SoC Design Training Program / Advanced Course:

Abstract: Under the NEDO “Post-5G Information and Communication System Infrastructure Enhancement R&D Project / Human Resource Development / Advanced Digital SoC Design Training”, Tenstorrent USA, Inc. has been selected, in collaboration with the Leading-edge Semiconductor Technology Center (LSTC), to participate in the project. As part of this initiative, Tenstorrent will conduct an advanced semiconductor design training course focused on single-nanometer semiconductor design. The program will primarily involve On-the-Job Training (OJT) in Silicon Valley, providing practical experience in cutting-edge semiconductor design. In this session, we will introduce Tenstorrent’s company profile, an overview of our RISC-V CPU and AI accelerators, and provide details about the human resource development project. 

Mamoru Nakano | President & CEO, Tenstorrent Japan Inc. (USA)

17:10-17:20

TBD

TBD

Andes Position Statement in the Japanese Region

Abstract: Andes worldwide position in RISC-V industry will first be reported. With Andes’ leading position, we aim to bring our competitive RISC-V solutions to the Japanese market, helping various Japanese industries—including system, machinery, communication, software, semiconductor, chip, and IC design service industries—achieve success. We will share “what” and “how” proposals in this regard.

Frankwell Jyh-Ming Lin | CEO and Chairman, Andes Technology (Taiwan)

17:45-17:50

RISC-V Day Tokyo 2025 Autumn Information

Presenter | Position, Affiliation (Region)

J

Withdrawal