13:00-
13:10

Words of Welcome

Linux on RISC-V Software Ecosystem:

Abstract:　The presenter will discuss (1) The status of Fedora/CentOS on RISC-V including the repo status and software supported RISC-V dev boards (10 min)
(2) Providing the status of current Firmware (OpenSBI/UEFI/uboot) and the kernel(5 min)
(3) Status for other Linux distros on RISC-V , like Arch-linux, Gentoo(5min)

13:45-
14:05

The Innovation features of RV64ILP32 Linux V3 patches

Abstract:　Guided by the RISC-V Profiles, the market has witnessed a surge in RVA(B) Profiles-based SoCs and CPU IPs deployed in resource-constrained environments with limited TCM, cache, and memory. Adopting the legacy LP64 ABI poses significant challenges in real-time responsiveness, performance, and cost control.

Hence, we implemented RV64ILP32 Linux to help these chips’ productization. Compared to history implementations, this version gives out full functionality Linux porting. Such as support 64lp64 applications, and a lot of rv64 specific features. We would give out the demo during the presentation and welcome to join the project.

Guo Ren | Staff Engineer, linux cpu subsystem, Alibaba  | Linux csky Maintainer (China)

OpenEuler for 2025: The Beginning of a RISC-V Server Platform Distro

Abstract: The Institute of Software, Chinese Academy of Sciences (ISCAS) has demonstrated significant advancements in RISC-V ecosystem development since 2022. The OERV team led by ISCAS has achieved comprehensive support for the RISC-V architecture within the openEuler operating system, ensuring compatibility with diverse hardware platforms.

In the first half of 2024, OERV reached a critical milestone by releasing the openEuler RISC-V 24.03LTS, which formally elevated RISC-V to Tier-1 architecture status within openEuler. Concurrently, through collaborations with industry partners, OERV introduced pioneering solutions, including the inaugural RISC-V-powered “RuYi Book” laptop and RISC-V ROS robotic systems, both operating on the openEuler RISC-V platform.

Looking ahead to 2025, OERV will focus on aligning with the RISC-V Server Platform specification to develop standardized server systems, strategically positioning itself to address the emerging demands of the RISC-V server market.

20 min

Interface of the Pulp project for RISC-V core

Abstract:
SLMLET is a low-power System-on-a-Chip (SoC), which is a promising device for edge computing. It consists of a RISC-V core and area-saving embedded Field-programmable gate arrays (eFPGA) blocks called Scalable Logic Module (SLM). This paper presents a fabricated SLMLET chip and a developed HW/SW co-design flow. The experimental results demonstrate that the RISC-V core can operate at up to 300MHz, and a hardware design on the SLM blocks can operate at up to 100MHz. By offloading compute-intensive processes to dedicated circuits implemented in the SLM blocks, it is possible to achieve up to 77 % energy reduction compared to software processing on the RISC-V core and other commercial microcontrollers.

15:00-15:20

20 min

Development of a library characterizer for utilizing self-made cell libraries in open semiconductor design

Abstract: Many open semiconductor designs and the open EDA and design environments that support them have been proposed, but these environments are based on the premise that circuit design will be performed using cell libraries provided by specific fabs. To load a self-created cell library into these environments, a characterizer is required, which is an EDA that characterizes the cell library by extracting its delay and power characteristics and creating a library. Here, we report on the current development status of the open source implementation of the characterizer that we are developing.

{Intermission} Bio Break

CHERI ALLIANCE 101

Takaaki Akashi | Country Manager – Japan, Codasip GmbH (Germany)

Title: CHERI alliance: embedding improved security in electronic systems

Abstract:
The CHERI alliance aims to mitigate memory safety problems through the adoption and dissemination of CHERI technology. Vulnerabilities due to memory safety take up more than two-thirds of all vulnerabilities in our world where cyber-security is an ever-increasing cost. CHERI solves this by adding bounds and permission meta-data to memory pointers, and the CHERI alliance is a neutral body where its members can pull together to promote, align and support CHERI adoption.

Bio:
Dr Marno van der Maas completed a PhD at the University of Cambridge in 2022 on protecting trusted execution environments from side-channel attacks. During this time, Dr Van der Maas also worked on implementing and testing processors that enforce bounds and permissions on memory pointers using a technology named Capability Enhanced RISC Instructions (CHERI). At lowRISC CIC, Dr Van der Maas is a principal hardware engineer working on the Sonata CHERIoT development platform, as well as on OpenTitan and Sunburst as a whole. His experience on verification and security enables him to contribute to the vision of making open silicon a reality.

E

Title: CHERI – Architectural memory safety and compartmentalisation full-steam ahead to commercialisation

Abstract: The CHERI Task Group was formed within RISC-V International to propose extensions supporting CHERI in the RISC-V ISA. The motivation of these extensions is to enhance RISC-V with features to address memory safety issues which account for over 70% of software vulnerabilities according to Microsoft’s Security Response Center (MSRC). In this presentation, we will provide an overview of the CHERI TG’s present and future work as well as the status of the specifications of the CHERI extensions.

Bio: Dr Jonathan Woodruff is a Senior Research Associate with expertise in processor architecture and microarchitecture as well as low-level software optimisation. Specialising in capability processor design, he has pushed into full-system optimisations including cache hierarchy, core timing, and multi-core designs as well as explorations into major security approaches including control flow integrity and private execution.

E

Title: Standardization of CHERI_RISC-V

Abstract: This presentation explains the trend of CHERI RISC-V standardization work. (TBU)

Bio: Tariq Kurd has over 20 years of CPU architecture, design and verification, mainly in the embedded space. I’ve worked on VLIW, multi-threaded, out-of-order cores, security and DSP style cores. I’ve been at Codasip 3+ years, and previously was at Huawei UK, Broadcom and Nvidia. Tariq was the chair of the Zfinx and Code Size Reduction Task Group of RISC-V International.

E

Title: CHERI – How it works

Abstract: This presentation will show how CHERI works with the Codasip X730 RISC-V Core FPGA Evaluation Kit in a storyboard format.

Bio: Successfully evangelized Verilog (IEEE std. 1364-1995) at Cadence at the start of the 1990s, and SystemVerilog (IEEE std. 1800-2005) and VMM, which is the archetype of UVM at Synopsys in the early 2000s, as a member of the JEITA (formerly EIAJ) standardization committee. Involved in semiconductor design in Japan for about 30 years. Four years as Codasip’s Country Manager – Japan.

E

13:00-15:30

SAIL-RISCV Memory Model Refactor

Abstract:　Sail-RISCV has been identified as the optimal model for the RISC-V ISA. However, it is important to note that the memory model of Sail-RISCV is subject to two primary limitations. Firstly, there is an absence of 34-bit physical address support in RV32, and secondly, there is ambiguity between physical and virtual memory. To address these deficiencies, a reconstruction of the Sail-RISCV memory model has been undertaken. Specifically, we employed new type constructs to distinguish physical and virtual memory, and enabled 34-bit physical address support by allowing arbitrary-width address mappings to Sail supported address types. We refined the communication mechanism with Sail’s simulated memory to accommodate arbitrary-width physical addresses, which are then mapped to corresponding Sail memory model addresses. Through experimentation, involving varying address widths, we validated the efficacy of this approach, demonstrating its correct handling of 34-bit addresses. The results of the study indicated enhanced type safety and improved model accuracy. A comparison of our implementation with alternative methods demonstrated that it offers greater flexibility, reducing the coupling risk between physical and virtual memory and providing a more precise memory abstraction for the Sail-RISCV model. For example, utilizing new type constructs ensures compile-time memory type safety. Experimental results confirmed our success in resolving type-safety concerns and extending Sail-RISCV’s support for 34-bit physical addresses. This enhancement, we believe, strengthens the accuracy of Sail-RISCV as a golden model for RISC-V. 

13:00-15:30

RuyiSDK – A Integrated and Customizable Toolkit for RISC-V Software Development

Abstract: The RISC-V instruction set’s design has given rise to a highly diverse ecosystem. However, the introduction of vendor-defined extensions has the potential to lead to fragmentation, creating challenges for developers in managing toolchains and adapting software. This paper presents RuyiSDK which is a comprehensive solution tailored for RISC-V developers. It is designed to address these challenges by integrating existing foundational software, promoting the adaptation of unsupported applications, and cultivating a vibrant developer community. RuyiSDK offers a package index that consolidates toolchains, emulators, and more, along with profile files that describe how to perform cross-platform builds, as well as software and RISC-V boards co-development. A key component of RuyiSDK is the Package Manager, which not only inherits the capabilities of traditional package managers but also incorporates advanced features such as virtual environment creation, device provisioning, and plugin support. The Package Manager transparently applies virtual environment profiles to the corresponding toolchains by reading the package index. Users only need to specify the target development board, without needing to manage toolchain differences manually. The device provisioning feature provides interactive guidance for keeping system images up to date for specific development boards, while test reports offer a certain level of quality assurance. The plugin system enables vendors and users to extend the Package Manager with custom features, thereby making it adaptable to various workflows. By providing a flexible, efficient, and transparent cross-platform development environment, RuyiSDK empowers developers to focus on innovation, thereby unlocking the full potential of RISC-V hardware while mitigating ecosystem fragmentation.

Weilin Cai,  Yilin Chen, Yunxiang Luo | Programming Language and Compiler Technology Lab, Institute of Software, Chinese Academy of Sciences (ISCAS) (China)

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Engaging the Next Generation: ISCAS’s RISC-V Education Through Short Video:

Abstract:　At the Institute of Software, Chinese Academy of Sciences, the internship program is dedicated to enhancing the education and promotion of RISC-V technology through innovative short video content. Projects like the “Understanding RISC-V” series simplify complex concepts and make them accessible, while hands-on demonstrations on platforms such as MilkV Duo and LicheePi engage a wide audience, including students, educators, and aspiring engineers.The process begins with interns conducting thorough research to identify gaps in existing RISC-V content. This groundwork informs the scripting and production phases, where interns blend technical information with practical demonstrations. These videos not only explain theoretical aspects but also highlight RISC-V technology’s practical applications, helps demystify subjects that can be intimidating to newcomers.Audience feedback plays a vital role in improving videos, ensuring they effectively meet the audience’s learning needs. This iterative process helps to crop content that is both informative and engaging.These videos serve as a stepping stone, guiding learners from basic principles to complex applications and fostering a deep understanding of RISC-V. This progression allows learners to advance at their own pace and explore in-depth topics as they grow more confident.This initiative supports ISCAS’s mission to integrate cutting-edge technologies like RISC-V into core educational curricula and promote active engagement with these technologies. By translating complex engineering concepts into accessible educational content, PLCT Lab is shaping a generation of engineers to thrive in a rapidly evolving technological environment and driving global adoption of RISC-V.

Fuyuan Zhang, Tianwei Jiang, Yunxiang Luo |  Programming Language and Compiler Technology Lab, Institute of Software, Chinese Academy of Sciences (ISCAS) (China)

UnityChip Verification Open-Source RISC-V verification at
BOSC

Abstract: The growing open-source hardware ecosystem presents a new opportunity to enhance hardware verification efficiency by involving a broader range of verification participants. As the software testing ecosystem has benefited from various tools and methods developed by its large community, this success offers a promising future for scaling out hardware verification by incorporating software testing developers. To support software developers in hardware verification, we propose three techniques to facilitate this integration: (1) providing state machine abstractions (cycle-accurate and looselytimed), (2) encapsulating hardware designs into software packages in multiple programming languages, and (3) introducing socket data transport and bidirectional direct function calls. These techniques are implemented on the CollabChip Verification (CCV) platform, enabling software developers and tools to engage in hardware verification workflows and collaborate with hardware engineers using hardware frameworks. We evaluate our methods on the XiangShan processor, demonstrating CCV’s effectiveness through case studies: software developers without hardware backgrounds uncover 11 bugs in two months. Zero-experience developers submit valid verification cases in 20 hours, and reducing average initiation time by 77% and enhancing existing verification environment with Python, accelerating the process by 16.6% and reducing lines of code by 12%

Xu An | Beijing Institute of Open Source Chip, Yunlong Xie, Zhicheng Yao | ” Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS)”

RISC-V Board and OS Support Matrix: A Comprehensive Resource for RISC-V Developers

Abstract: The current market offers a plethora of RISC-V boards, with numerous operating systems (OSes) available from both the boards’ manufacturers and the community. However, newcomers to RISC-V may encounter difficulties accessing current information regarding RISC-V boards and their OS support status.To address this need, this paper has initiated a support matrix project to assist RISC-V developers and enthusiasts. The RISC-V Board and OS Support Matrix is an open-source initiative that catalogues the compatibility between RISC-V development boards and operating systems, thereby responding to the growing requirement for a well-organised, readily accessible database to guide developers in selecting compatible software for their RISC-V hardware platforms. The initiative highlights areas requiring community assistance, such as configurations marked as “”Call for Help”” (CFH), “”Call for Testing”” (CFT), and “”Work in Progress”” (WIP).Additionally, it includes tools for metadata parsing and SVG generation, helping to maintain and visualize compatibility data.This initiative is part of the broader RuyiSDK project, which aims to provide a full-stack development environment for RISC-V. The initiative integrates tools such as a package manager and a graphical integrated development environment (IDE).By offering up-to-date hardware and software compatibility data, the initiative simplifies decision-making for developers and researchers in the RISC-V ecosystem. The RISC-V Board and OS Support Matrix has been developed to facilitate the installation of operating systems and software on RISC-V boards, thereby reducing the complexity of the process for novices and promoting the development of the RISC-V software ecosystem.

Jingkun Zheng, Yunxiang Luo | Programming Language and Compiler Technology Lab, Institute of Software, Chinese Academy of Sciences (ISCAS) (China)

RISC-V Appeal: The Growth Path from Students to Engineers

Abstract: With the implementation of various large AI models, optimizing AI model training and inference has become an increasingly important task. As the interface between high-level programs and low-level chip execution, the assembly instruction set plays a critical role in optimization and often becomes both a bottleneck and a breakthrough point in the process. RISC-V offers unique advantages in this area: it is an open-source instruction set, highly scalable, and has special support for vector computations. Therefore, leveraging the deployment environment of AI models can accelerate the development of the RISC-V ecosystem.Now, it is essential to raise awareness about the unique advantages of the RISC-V instruction set.First, we will promote the characteristics of RISC-V to the student community through various channels. By taking advantage of students’ enthusiasm for following trends, we will integrate modern online elements into video production to lower the learning threshold and increase engagement. These videos will be widely disseminated through social platforms and online education channels, quickly attracting student attention.Next, as students’ interest in the RISC-V instruction set grows, they will actively search for related technical videos. During this process, the in-depth technical content provided by PLCT will help students and engineers further understand the details and applications of RISC-V. Particularly, developing a RISC-V simulator will allow learners to intuitively grasp the fundamental principles of computer architecture and understand the process of hardware instruction execution. By guiding more students to participate in actual development, we can deepen their understanding of RISC-V and effectively boost the activity of the technical community, creating a **virtuous cycle** that will attract more young engineers to join the RISC-V ecosystem.Ultimately, this will foster a young, vibrant community of engineers who are passionate about RISC-V.
By taking advantage of RISC-V’s open-source nature and scalability, the deployment of large AI models will become a valuable opportunity for the development of the RISC-V ecosystem and community. It will also attract more students and engineers to contribute to its growth.

Xirui Hao, Fuyuan Zhang, Yunxiang Luo | Programming Language and Compiler Technology Lab, Institute of Software at the Chinese Academy of Science (China)

FCVT support for ACT through RISCOF

Abstract: As the number of RISC-V processor models continues to increase, verifying whether a RISC-V processor complies with the ISA specification has become an important issue. As the official testing tool used for ACT testing, RISCOF can leverage the Sail-RISCV model as a reference to check whether the tested model conforms to the specification. However, the ACT test repository used by RISCOF lacks support for many test instructions and extensions, including several test cases for the zfh extension, such as `fcvt.d.h`. Therefore, we will add new test instruction support to RISCOF to address this issue.RISCOF relies on multiple testing tools for test development. These include RISCV-CTG for generating test cases and RISCV-ISAC for coverage testing. To support new test instructions, we need to add YAML nodes for the test instructions in RISC-V CTG to define them and write corresponding CGF files for the instructions. Next, we will add the relevant instruction checks to the decoder in ISAC to support the coverage detection of the new instructions. Afterward, we will run RISCOF with the generated test cases, and the results will show that the test outcomes are accurate.By adding support for test instructions to ACT via RISCOF, we can provide greater flexibility for testing, further advancing the comprehensiveness and accuracy of ACT testing.

Zhu Xuchang, Luo Yunxiang | Programming Language and Compiler Technology Lab, Institute of Software, Chinese Academy of Sciences (ISCAS) (China)

RISC-V in Education:Empowering the Next Generation of Engineers through Open-Source Learning Platforms

Abstract: With the rapid development of computer technology,training a new generation of engineers has become an important task in the field of education.Traditional educational models often fail to provide students with a comprehensive understanding of the interaction between hardware and software.Therefore,introducing the open-source architecture of RISC-V can offer students a more practical and innovative learning platform to quickly grasp the core knowledge of computer architecture.This paper adopts the RISC-V open-source architecture as an educational tool and apply it to the teaching of computer architecture and hardware design.The open-source nature of RISC-V allows students to directly engage with the design of computer hardware and quickly understand the interaction and communication mechanisms between the lower and upper layers.As a result,through the study of cross-compilation,operating systems,and related knowledge,students can gain a better understanding of compilers and other relevant content.By introducing RISC-V into the educational field,engineers provide students with an efficient and open learning platform to help them quickly master the key skills of computer architecture and hardware design.This educational initiative not only enhances students’technical capabilities but also provides strong support for training a new generation of engineers,laying a solid foundation for future technological innovation and industry development.

Zhi Li, Fuyuan Zhang, Yunxiang Luo | Programming Language and Compiler Technology Lab, Institute of Software, Chinese Academy of Sciences (ISCAS) 

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Open Source Hardware and RISC-V:Bridging the Digital Divide and Advancing Social Equity through Cost Reduction and Innovation

Abstract: With the rapid development of computer technology,training a new generation of engineers has become an important task in the field of education.Traditional educational models often fail to provide students with a comprehensive understanding of the interaction between hardware and software.Therefore,introducing the open-source architecture of RISC-V can offer students a more practical and innovative learning platform to quickly grasp the core knowledge of computer architecture.This paper adopts the RISC-V open-source architecture as an educational tool and apply it to the teaching of computer architecture and hardware design.The open-source nature of RISC-V allows students to directly engage with the design of computer hardware and quickly understand the interaction and communication mechanisms between the lower and upper layers.As a result,through the study of cross-compilation,operating systems,and related knowledge,students can gain a better understanding of compilers and other relevant content.By introducing RISC-V into the educational field,engineers provide students with an efficient and open learning platform to help them quickly master the key skills of computer architecture and hardware design.This educational initiative not only enhances students’technical capabilities but also provides strong support for training a new generation of engineers,laying a solid foundation for future technological innovation and industry development.

Zhi Li, Fuyuan Zhang, 
Yunxiang Luo | Programming Language and Compiler Technology Lab, Institute of Software, Chinese Academy of Sciences (ISCAS) (China)

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Comparative Analysis of Compiler Performance for RISC-V on SPECCPU2017

Abstact: Using instruction count as a metric, we employed SPEC CPU 2017 to compare the performance of programs compiled with GCC and LLVM on RISC-V, with a particular focus on the RISC-V vector extension. Benchmarks were run in parallel using QEMU, enabling large-scale testing. The analysis showed that tests compiled with LLVM executed more instructions than those compiled with GCC for both INT Rate and FP Rate. After enabling the vector extension, the gap in FP Rate narrowed significantly, suggesting that LLVM’s auto-vectorization performs better in certain scenarios.
In the 548.exchange2_r benchmark, tests compiled with LLVM executed 105% and 95% more instructions than those compiled with GCC on scalar and vector targets, respectively. We conducted further investigations into this issue and ultimately developed a patch about LLVM’s IPSCCP Pass, which significantly reduced the instruction count by 40% for this specific benchmark. Additionally, the patch did not introduce any side effects on other tests. The observed data still contains many aspects worth exploring further.
This study demonstrates the feasibility of using SPEC CPU 2017 to evaluate compiler performance on RISC-V. It also highlights its potential for testing feature optimizations and ISA-specific extensions, providing insights for further investigations and compiler performance improvements.

Yongtai Li, Chunyu Liao
Ji Qiu | Programming Language and Compiler Technology Lab, Institute of Software at the Chinese Academy of Science (China)

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V8 for RISC-V in 2024: What’s new

Abstract: This poster summarizes the progress of the Chromium V8 JavaScript engine for RISC-V architecture in 2024. PLCT Lab, the maintainer of the V8’s RISC-V backend, contributed over 17,000 lines of code in a total of 173 patches, which has the 5th rank among all the contribution teams. First, new JavaScript and WebAssembly (Wasm) language features were added, including managed objects and garbage collection for Wasm, enhanced API calls, and improved stack management. Second, general performance enhancements were achieved through pointer compression, a new just-in-time compiler (Maglev), optimized indirect calls in Wasm, and security features like a configurable sandbox and Control Flow Integrity (CFI). Thirdly, significant optimizations were implemented, leveraging RISC-V ISA extensions to improve jump and builtin code generation, and reduce code size. Finally, support for SV39/SV48 configurations and multicore environments was added, including I-cache flushing. Benchmark results demonstrate the notable performance improvements. Future work includes continuously tracking upstream and expanding support for features like LeapTiering and Maglev.

Yahan Lu, Ji Qiu | Programming Language and Compiler Technology (PLCT) Lab, Institute of Software Chinese Academic of Sciences

Optimizing Data Transport Architectures in RISC-V SoCs for AI/ML Applications

Abstract: This presentation will illustrate the challenges and solutions of data-transport architectures for artificial intelligence/machine learning (AI/ML) in the context of embedded vision architectures and discuss implementation aspects for Networks-on-Chips (NoCs) for RISC-V-based System-on-Chips (SoCs). AI/ML and Embedded Vision architectures present unique challenges in data transport architectures to procure all relevant data from off-chip DRAMs and efficiently store and transport them in caches to allow efficient computing on SoCs and systems of chiplets. These challenges directly translate into specific requirements for NoC implementation, impacting performance, power consumption, and cost, efficiently addressing the challenges posed by what the industry calls the “”memory wall”” – the much faster improvement of processor vs. DRAM memory access speed. In addition, for the automotive and industrial application domains, special considerations regarding safety and resilience need to be considered to allow for ISO26262 and related certifications. 

Michal Siwinski, Guillaume Boillet, John Min | Arteris (USA)

Development of a System for Easy Utilization of RISC-V Extensions Using Hypervisor Technology

Abstract: In RISC-V, modular specifications called “extensions” are being developed one after another. However, many of these extensions remain unutilized because hardware implementations have not kept pace, leaving them in a suspended state.
This study proposes a system that emulates RISC-V extensions as modular functionalities on a hypervisor, enabling the easy deployment of an environment that supports hardware extensions. By installing modules corresponding to the desired RISC-V extensions into the proposed system, users can effortlessly introduce new extension environments to their existing hardware.
The system was developed from scratch and successfully traps and emulates exceptions caused by newly defined instructions and CSRs in the hypervisor, making guest software perceive that the hardware supports those extensions. Additionally, a tool was developed to automatically generate hypervisor module and decoder implementations using Sail, a language for describing ISA specifications.
To demonstrate the usefulness of the proposed system, we emulated the Zicfiss extension, which provides a shadow stack, and conducted attack validation experiments in a Linux environment. Furthermore, a demonstration on actual hardware is planned.

Norimasa Takana, Yoshihiro Oyama | University of Tsukuba (Japan)

The choice and dilemma of integrated GPU solutions for RISC-V platform

Abstract: This time, I will focus on the business development of Imagination, a major IP provider in the field of integrated GPUs for RISC-V platforms, the trends for developers and their clients, the difficulties in adapting Linux distributions, and IMG’s most criticized technical support. I will also bring you information about the “Nijigasaki High School Imagination Club” hosted by us. 

Jingyu Pu | PLCT Lab (Programming Languages and Compilation Technologies Lab) (China)

RevyOS: Optimizing Debian for XuanTie Chip Ecosystem – Challenges and Achievements in RISC-V Adaptation

Abstract: RevyOS is a tailored Debian-based distribution specifically optimized for the XuanTie chip ecosystem, developed and maintained by the RevyOS team, a subgroup within the RuyiSDK team. This presentation will explore the challenges and methodologies involved in adapting Linux distributions for diverse RISC-V hardware platforms, and introduce the current accomplishments of RevyOS.

Han Gao, Xuan Chen | PLCT Lab 

From Vector to Matrix: The Future of RISC-V Matrix Extensions

Abstract: The idea of accelerating the emerging matrix workloads from artificial intelligence and machine learning has been implemented in general-purpose ISA including x86-64 (AMX) and ARMv9.2 (SME), and accelerators including NVIDIA Tensor Cores. RISC-V, as an open-source ISA, has followed this trend a multiple matrix extension drafts and implementations available. In this poster, we’ll introduce the Integrated matrix extension from Spacemit and the Attached Matrix Extension from Xuantie, Stream Computing, and SiFive (Zvma). We’ll focus on the tradeoff between “”Integrated”” and “”Attached””, the relationship between existing V extension and matrix extension, and the potential hardware implementation of RISC-V matrix acceleration in this poster.

Yan Lu | University of Tokyo

Efficient Transposed Matrix Multiplication in DNN Training Using Custom RISC-V Vector Extensions

Abstract: In Deep Neural Networks (DNNs), optimizing matrix operations is crucial for enhancing performance and energy efficiency. The open-source RISC-V instruction set architecture (ISA) supports vector extensions that accelerate data-parallel algorithms. In this work, we propose a new approach for efficient transposed matrix multiplication in DNN training by introducing a dot-product instruction alongside existing vector multiply-add instructions in RISC-V.

During backpropagation, the matrix from the forward pass must be transposed. Although it is possible to perform transposition by accessing data in a different order without actually moving data in memory, this typically requires vector loads from non-contiguous addresses, making latency hiding more difficult compared to contiguous vector loads. We therefore focus on how matrix elements are oriented in registers for vector multiply-add and dot-product operations, thereby enabling the execution of transposed matrix multiplication in backpropagation while using only contiguous-address vector loads.

The hardware resources for the proposed method were evaluated through an FPGA implementation, demonstrating that the same functional units can be shared by both vector multiply-add and dot-product operations. The result of multiplying a row-major matrix by a column-major matrix using the implemented core showed that the dot-product approach reduced the required number of cycles compared to combining vector multiply and vector reduction-sum instructions, while also reducing memory accesses compared to the vector multiply-add approach. These findings highlight the potential of dot-product instructions to optimize DNN workloads on RISC-V vector processors.

Riku Ando | Kawahara Laboratory, Department of Electrical Engineering,
Tokyo University of Science, Japan

RISC-V based AI Accelerator design using approximate arithmetic processing elements

Abstract: Research and development (R&D) on Artificial Intelligence (AI) has increased exponentially in recent years. Along with this, power demand for AI tasks has also been growing at an unprecedented rate, which has led to an increase in R&D efforts in hardware dedicated to AI applications. This poster and demonstration present an artificial intelligence (AI) accelerator design using approximate arithmetic processing elements (PEs), in collaboration with Cassia.ai with their approximate arithmetic technology and systolic array implementation, to perform hand-written digit recognition tasks using the LeNet convolutional neural network (CNN). Instead of using traditional, absolute arithmetic for PEs within the systolic array, this design proposed adapting approximate arithmetic for these PEs. This proposal is based on the fact that most AI and deep learning implementations use approximate calculations to reduce the complexity of the model, such as regularization, feature selection, and dropout, thus reducing power consumption. This design employs UC Berkeley’s Chipyard design framework and UC Berkeley’s Gemmini systolic array as the technology base to demonstrate approximate arithmetic technology. Preliminary tests with the LeNet model have shown no significant reduction in prediction accuracy, as well as performance when compared with the original Gemmini systolic array design.

Ngoc Lam Nguyen, Trong-Thuc Hoang, Cong-Kha Pham | University of Electro-Communication

An Extension of Ripes RISC-V Simulator

Abstract: Ripes is a graphical processor simulator
for the RISC-V instruction set architecture.
It visualizes the various operations among microarchitectural
components for the execution of each instruction.
It should be a good alternative for other processor
simulators, such as spim, when RISC-V is used as the base
of studying the computer architecture.

In this project, we focus on the software-hardware
interactions in the RISC-V based system.
In particular, visualization of the stack segment is
added to the Ripes simulator for better understanding
of how function calls are implemented.
The stack segment is used for passing function calling arguments,
local variables within the invocation of the function,
and the return address to the caller function.

We have added a tab for the stack in Ripes to
display these information. By utilizing the information
from libdwarf, the local variable names are retrieved and
included in the stack tab. This debugging information
from libdwarf is also utilized for showing the calling function
name next to the return address in the call frame.
A table for showing the frame of the function call is created
for each invocation, and it is removed on the return
from the function.

In addition to the original execution control buttons,
such as Clock or Run, we have added the C-Step button, which
keeps Ripes running until the execution of the RISC-V
instructions for the current C-source code line are finished.
With this button, we can move to the instruction of the interest
quickly.

Hitoshi Oi, Daichi Higashi | The University of Aizu

RISC-V-based Multicore Processor for Multi-threading: Hardware to Software Design Perspective

Abstract: This research explores the design of a RISC-V-based multicore processor system tailored for the data-centric era, bridging the gap between general-purpose and special-purpose architectures. Recognizing the limitations of traditional approaches in handling big data, the research emphasizes a co-design approach involving both hardware and software.

The proposed architecture features a high-performance core that generates threads distributed to other cores via a thread queue. Private working spaces and bi-directional private buses minimize shared resource contention and data movement overhead. A key innovation is the integration of near-cache processing capabilities through a hybrid L1 cache, functioning as both cache and local/shared memory for tightly-coupled accelerators. This allows data to be processed closer to memory, maximizing bandwidth utilization.

Benchmark results on matrix multiplication achieve a 4-6x speedup with a four-core configuration and a 6-18x speedup with an eight-core configuration. The tightly-coupled accelerators, leveraging the hybrid L1 cache, achieve remarkable speedups ranging from 24x to over 177x compared to a single core.

Binh Kieu-Do-Nguyen, Khai-Duy Nguyen, Cong-Kha Pham, Trong-Thuc Hoang | 

An evaluation of multi-core and V extension RISC-V processor

Abstract: The multi-core processor architecture has been ubiquitous as the computing workload becomes more complex, especially on well established systems based on ARM or x86. The servers, PCs and even mobile devices have already adopted parallelism for improved performance since the early 2000s to improve performance on various workloads such as 3D Rendering and video transcoding. There are two approaches to parallelism on a CPU processor, namely multi-core and SIMD (Single-Instruction-Multiple-Data). RISC-V is an open instruction-set architecture which supports both multi-core and SIMD via V extension. However, there is a shortage in the number of benchmarks that target parallelism approaches on RISC-V based system, making comparison between the implementations difficult. Therefore, a method to evaluate the scalability of a RISC-V system is crucial. This work aims to perform performance evaluation on these on both multi-core and V extension enabled RISC-V based system. For the multi-core system, RV32IMAC (1-16 cores) and RV64GC (1-8 cores) Rocket Core are generated using the Chipyard framework on Xilinx VC707 FPGA platform. Under Linux software environment, a synthetic benchmark suggests that it achieves linear performance speedup as the number of cores increase, however, for a more specific workload such as graph coloring, the speedup is only 8.32x for 16-cores RV32IMAC configuration and 5.84x for 8-cores RV64GC configuration, respectively, compared to the single core variants. On the other hand, for a RISC-V core with V extension Zve32x with VLEN 128, the initial benchmark shows that it can benefit image processing workload at a speedup of up to 20x compared to the scalar core.

The-Binh Nguyen, Trong-Thuc Hoang, Cong-Kha Pham | University of Electro-Communications (UEC), Tokyo, Japan 

Development of a library characterizer for utilizing self-made cell libraries in open semiconductor design

Abstract: Many open semiconductor designs and the open EDA and design environments that support them have been proposed, but these environments are based on the premise that circuit design will be performed using cell libraries provided by specific fabs. In order to load a self-created cell library into these environments, a characterizer is required, which is an EDA that characterizes the cell library by extracting its delay and power characteristics and creating a library. Here, we report on the current development status of the open source implementation of the characterizer that we are developing.

Shinichi Nishizawa | Waseda University/ISHI-KAI