11:45-
12:10

Reception and Admission: {Press Business Card Exchange Event} (Invitation Only)

12:10-
12:15

Welcome Remark: {Press Business Card Exchange Event} (Invitation Only)

12:15-
12:45

Socializing: {Press Business Card Exchange Event} (Invitation Only)

12:45-
12:50

Closing Remarks: {Press Business Card Exchange Event} (Invitation Only)

12:50-
13:00

Opening, Cleanup, and Changeover: {Press Business Card Exchange Event} (Invitation Only)

13:00-
13:10

Master of Ceremony’s Words of Welcome

JASA RISC-V Chip Project

13:40-
14:00

ISHI-Kai Open Silicon Activities and Invitation to Small Scale Chip Tapeout Opportunities: ISHI-KAI is a community-driven project that promotes open-source Process Design Kits (PDK) and Electronic Design Automation (EDA) tools. The initiative focuses on collaborative semiconductor design, bringing together novice designers to create individual analog circuits like inverters and operational amplifiers using tools such as xschem and klayout. These individual projects are then integrated into a single layout for fabrication.

 Noritsuna Imamura | ISHI-KAi

20 Minute Reseating | Bio Break

Linux on RISC-V Software Ecosystem: (1) The status of Fedora on RISC-V including the repo status and software supported RISC-V dev boards (5 min) e.g. firefox, libreoffice, Thunderbird, chromium, (2) Providing the status of current Firmware (OpenSBI/UEFI/uboot) and the kernel status on RISC-V software ecosystem (5 min), (3) Status for other Linux distros on RISC-V , like Arch-linux, Gentoo(5min)

Wei Fu | RISC-V Ambassador @ RISC-V Foundation, Principal Software Engineer @ Platform Enablement, Red Hat Software (Beijing) Co.,Ltd.

Jiachen Project: RISC-V Prosperity 2036 (甲辰计划): The Jiachen Project: RISC-V Prosperity 2036, also known as 甲辰计划, is an ambitious initiative aimed at significantly advancing the RISC-V ecosystem by the year 2036, the next Year of the Dragon. This project is spearheaded by ASE Labs, PLCT Labs, and Sophgo, among other key players in the RISC-V community

Wei Wu | RISC-V Ambassador @ RISC-V Foundation, The co-founder and project director of PLCT Lab

15:00-
15:20

E

Canaan Kendryte K230D: The first rv64ilp32 Product for AIoT: The Canaan Kendryte K230D is the first rv64ilp32 product, balancing 64-bit processing advantages with the memory efficiency of 32-bit data types. It is suitable for various smart hardware products, including security-enhanced smart door locks, real-time surveillance home security cameras, and high-performance drones. 

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20 Minute Reseating | Bio Break

E

Technical Advantages of RISC-V in Shell-Role Type Chips: Shell-Role type chips represent a new chip architecture composed of a fixed logic Shell part and a flexible Role part. Examples of this architecture include the SLMLET in the CREST project and a test chip in the Agile-X project. The SLMLET incorporates an FPGA IP proposed by Kumamoto University in the Role part. Meanwhile, the Agile-X project employs a gate array in this part, enabling the realization of an ASIC configuration quickly and cost-effectively using Minimal Fab. This report compares the features of both examples and discusses their future potential.

E

Scalable AI Hardware Accelerator with Secured Network-on-Chip Framework:  This presentation will explain the development of RISC-V-based scalable AI hardware accelerators and secure Network-on-Chip (NoC) frameworks. It will explore architectures and design principles that ensure robust security measures within the NoC while achieving efficient AI computation. Topics include custom extensions leveraging the flexibility of RISC-V, implementation strategies for performance optimization, benchmark results, and security protocols integrating trusted execution environments (TEE) and cryptographic accelerators to safeguard data integrity and confidentiality. The presentation will also share insights from the design automation and evaluation environments at the University of Electro-Communications (UEC) and discuss the technical advantages and future potential of collaborations with domestic and international research institutions and companies.

E

Activities of AI chip design center: AIST and the University of Tokyo jointly operate an AI chip design center to support the development of semiconductor chips such as AI chips in Japan. From FY2019 to FY2022, the base was constructed as part of the NEDO project, and trial operations were also conducted in parallel. From FY2023, it will be positioned as a shared facility of AIST, and independent operation will begin. In this lecture, we will introduce the LSI design infrastructure and SoC platform that the AI ​​Chip Design Center has developed and provided, as well as the future development of the AI ​​Chip Design Center.

E

Kuniyasu Suzaki | Professor , Graduate School of Information Security, Institute of Information Security (IISEC)：
TS-Perf: Performance measuring method in the TEE (Trusted Execution Environment) of various CPUs.
Abstract: The Trusted Execution Environment (TEE) is implemented in many CPU architectures. Intel has SGX, Arm Cortex-A has TrustZone, and RISC-V has Keystone. While OS-equivalent software is executed in Arm TrustZone and RISC-V Keystone, Intel SGX executes at the library level within the TEE, resulting in significant differences in implementation architectures. Consequently, it is challenging to measure execution time within the TEE and compare performance with execution on the OS outside the TEE. TS-Perf addresses these discrepancies, allowing for the comparison of the same binary execution within the TEE and on a regular OS. Comparisons using TS-Perf have made performance differences within the TEE clear.

E

11:35-
15:00

RISC-V System-on-a-Chip with ASCON Cryptography for IoT applications on 180nm CMOS: The number of IoT devices has grown significantly in recent years, and edge computing in IoT is considered a new and growing trend in the technology industry. While cryptography is widely used to enhance the security of IoT devices, it also carries limitations such as resource constraints or latency. Therefore, lightweight cryptography (LWC) balances commensurate resource usage and maintaining security while minimizing system costs. The ASCON stands out among the LWC algorithms as a potential target for implementation and cryptoanalysis. It provides authenticated encryption with associated data (AEAD) and hashing functionalities in many variants, aiming for various applications. In this brief, we present an implementation of ASCON cryptography as a peripheral of a RISC-V System-on-a-Chip (SoC). The ASCON crypto core occupies 1,424 LUTs in FPGA and 17.4kGE in 180nm CMOS technology while achieving 417Gbits/J energy efficiency at a supply voltage of 1.0V and frequency of 2MHz.

Are we, uh, screwed?: An Overview in RISC-V Vector Extension in 2024: From the instruction design perspective, does RVV have its advantage compared to SIMD, NEC SX, and SIMT under different VLEN and workloads? Processor design in RVV is also negatively influenced by pipeline dependency and long vector handling.
   The RVV has broken its instruction backward compatibility for V0p7 (XTheadVector) and V1p0 now, while vendor extensions to V make things worse. Besides the instruction set, the intrinsic compatibility has been abandoned multiple times, which makes software porting a nightmare.
   The Software Stack makes most problems here. The compiler engineers and libraries author still need to work on processor-based optimization originally claimed to be shared between different designs. Multiple workaround solutions in Operating Systems like RevyOS, and multi-feature supporting binary, have to support different feature sets and code paths and deal with hardware errata, which stalls a usable baseline distribution here.
   When it comes to actual hardware design, things get even worse. In embedded designs,
V is too heavy while P (as a 1990s MMX-level design) makes no sense for the current situation. In Desktop designs, we can easily state that hardware and software are not ready. In HPC designs, which seem to be the most promising, multiple designs have been issued. But as a solution, it might not be mature for a lack of toolchain optimization and software stack.
   So, if we do not cooperate in dealing with RVV, then RVV as a general-purpose extension is dispensable.

Presenter: Yan Lu | Graduate School of Frontier Sciences, The University of Tokyo (Chiba, Japan),  Yangyu Chen | Chongqing University (Chongqing, China),  Yang Man | Institute of Computing Technology (Beijing, China), China Academy of Science,  Yingwei Zheng | Southern University of Science and Technology (Shenzhen, Guangdong, China)

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Development of a System for Easy Utilization of RISC-V Extensions Using Hypervisor Technology: In RISC-V, modular specifications known as “extensions” are being formulated one after another. However, the hardware implementation has not progressed as expected, leaving many extensions unused and in a state of limbo.
   While some specifications, such as the Vector extension, rely on specialized hardware, many involve custom instructions and the addition of CSRs, which can often be replicated by a hypervisor.
   In this research, we will reproduce RISC-V extensions in modules on a hypervisor and develop a system that can be managed in software.
Emulation is achieved by trapping the newly introduced instructions, CSRs, exceptions, and memory areas on the hypervisor side.
   Users can easily introduce new extension environments to their hardware by installing modules that correspond one-to-one with the desired RISC-V extensions into the proposed system.
   This facilitates easier use of RISC-V extensions for users and provides developers with valuable feedback, promoting the formulation of specifications and the implementation of toolchains.
   As the user base grows and the software toolchain becomes more fulfilling, it is expected that developers will emerge who implement extensions in hardware based on demand.
   The system’s objectives are twofold: to support the utilization of existing suspended extensions and accelerate ecosystem development, and to create hypervisor modules that describe system functions linked to RISC-V specifications.
   This research not only enables the addition of specifications and functionalities to the RISC-V system via a hypervisor but also challenges the current state and future direction of RISC-V specifications and the ecosystem being continuously formulated.

Norimasa Takana | University of Tsukuba,Yoshihiro Oyama | University of Tsukuba

A triple modular redundant RISC-V processor on a Cyclone V FPGA: Under a strong radiation environment such as decommissioning situation of nuclear power plants, radiation-hardened processors are needed for robots and other systems. Currently, space-grade processors are available. However, even if we use such space-grade processors, the radiation tolerance is not sufficient in Fukushima Daiichi Nuclear Power Plant. The life-time of the space grade processors is limited to about 10 hours. So, we introduced triple modular redundancy (TMR) for a RISC-V processor to increase the total-ionizing-dose tolerance.
   The RISC-V processor mainly consists of a TMR program counter, TMR register file, TMR Arithmetic Logic Units (ALU), TMR instruction memory and TMR data memory. All units have majority voting circuits which can be executed automatically at every clock cycle. Even if one of three modules doesn’t work, the rest two modules can generate a correct result. The TMR RISC-V processor has been implemented onto a Cyclone V Field Programable Gate Array (FPGA) on a DE1-SOC FPGA board. We have confirmed all the operations of basic RISC-V instructions. The maximum operating frequency was measured as 64.82 MHz. The FPGA’s resource usage was 45 %.

Masato Isobe | Graduate school of Environmental, life, Natural Science and Technology, Okayama University, Mioru Watanabe | Faculty of Environmental, Life, Natural Science and Technology, Okayama University, Nobuya Watanabe | Faculty of Environmental, Life, Natural Science and Technology, Okayama University

Poster Presentation 65

TBD

Poster Presentation 66

TBD

Linux Capable RISC-V SoC with OpenXC7 for Educational Purposes: RISC-V softcores are widely available, but most cores capable of running Linux are complex and therefore unsuitable for educational purposes. We want to present QuasiSoC, a 32-bit RISC-V CPU and SoC written in pure Verilog that runs the mainline Linux kernel in MMU and no-MMU modes. The 32-bit no-MMU support has been implemented for the first time and has now been added to the Linux kernel and buildroot upstream. The easy-to-understand code, BRAM-like bus interface, and optional memory management unit make it an optimal choice for educational scenarios. QuasiSoC typically utilizes only 25% of the logic resources in the AMD/Xilinx Artix 7 xc7a35t FPGA with SDRAM, HDMI, and SD card features enabled. Thus, it is compatible with the majority of budget-constrained educational development boards.
   The SoC is fully supported by OpenXC7, an emerging free and open source FPGA toolchain for AMD/Xilinx 7-series chips, promoting the importance of free/libre software in hardware and education over proprietary tools.
   The SoC also runs on FPGAOL, an online educational FPGA cluster service hosted by the University of Science and Technology of China (USTC), which allows users to interact directly with real Artix 7 FPGAs via a browser. The SoC will be used in the university’s embedded development courses.

Yimin Gu (The University of Tokyo), Xu He (The University of Science and Technology of China), Xingyan Chen (The University of Science and Technology of China), Shicheng Zheng (The University of Science and Technology of China), Jianliang Lu (The University of Science and Technology of China)

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Poster Presentation 68

TBD

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Hardware/Software Co-Design of Thread-enabled RISC-V-based Multicores: Since its inception in 2011, RISC-V has experienced tremendous growth, resulting in numerous free and open-source processors based on its instruction set. RISC-V is increasingly used in various devices like IoT, wearables, and AI, creating a demand for multicore platforms built with RISC-V cores. While combining different RISC-V cores for specific applications seems ideal, it’s challenging because most open cores lack features needed for efficient multicore design. This research proposes a hardware/software co-design solution to overcome these bottlenecks, significantly improving the performance of multicore systems.

Do Nguyen Binh Kieu（The University of Electro-Communications）Japan,
Khai Duy Nguyen （The University of Electro-Communications） Japan ,
Tuan Kiet Dang （The University of Electro-Communications） Japan ,
Cong-Kha Pham （The University of Electro-Communications） Japan ,
Trong-Thuc Hoang （The University of Electro-Communications） Japan

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DynamoRIO for RISC-V: Implementation and Porting Progress:  DynamoRIO is a dynamic code transformation system renowned for its versatility in applications such as program analysis, profiling, instrumentation, and more.
   Currently, it supports x86, x86-64, ARM, and AArch64 architectures, with ongoing porting efforts for RISC-V demonstrating significant progress. A portion of the core APIs has been successfully ported to RISC-V, and multiple clients are working well now. 

Dr. Yang Liu, Precision Logic and Computational Technologies Laboratory (PLCT Lab) , Tsinghua University, Beijing

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開場

歓迎の挨拶

歓談

TBD

閉会

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