(Abstract Deadline July 20, 2024)
Thursday, August 1, 2024
8:00-18:00 Japan Standard Time JST (UTC+9)
Click Here to Register for the Event
Ito International Research Center, The University of Tokyo
Contents Categories |
① RISC-V Solutions |
② Special Sessions:Japan’s Semiconductor Strategy 2024 and RISC-V |
③ RISC-V Lunch Meetings |
④ RISC-V Technical Exhibits |
⑤ RISC-V Research and Open Semiconductors |
⑥ AI、RISC-V Research Poster Session |
The RISC-V Day Tokyo conference is the largest RISC-V event in Japan. The RISC-V Day Tokyo 2024 Winter conference will be held on Tuesday, August 1, 2024 from 9:00-17:00 JST (UTC+9) at the Ito International Research Center, The University of Tokyo. We will bring together excellent RISC-V-related technologies and products, as well as key people and engineers, and provide business opportunities such as increasing product awareness, realizing collaboration between companies, technology exchange, and information gathering. We look forward to your participation on this occasion! A video of the presentation and information on materials will be posted on the website at a later date.
① RISC-V Solutions ② Special Event: Japan’s Semiconductor Strategy 2024 & RISC-V ③ RISC-V Lunch Party
August 1, 2024 Time: 8:00-18:00
Chair: SH Consulting, Haruyuki Tago
The names, contents and times of lectures may be changed depending on the circumstances.
Time | Minutes | Language | Presentation Topic | Presenter | Organization | 講演資料 |
---|---|---|---|---|---|
8:00-8:40 | 40 min | – | Reception: Name badges, bottled tea, and the book “Japan’s Semiconductor Strategy 2025 Preview Edition” distributed | Recording Equipment Audio-Visual Setup | |
8:40-8:55 | 15 min | JE | “Japan’s Semiconductor Strategy 2025” Overview | Haruyuki Tago | Editor of “Reading Japan’s Semiconductor Strategy 2024” | SH Consulting K.K. | – |
9:00-9:20 | 20 min | J | Invited Lecture: Current Status of Japan’s Semiconductor and Digital Industry Strategy (tentative) | Hisashi Saito | Deputy Director, IT industry division, Commerce and Information Policy Bureau, Ministry Economy, Trade and Industry | – |
9:25-9:55 | 30 min | E | Expansive Applications of Tensorrent RISC-V AI and RISC-V CPU | Wei-Han Lien | Lead CPU Architect, Tenstorrent (Canada) | – |
9:55-10:25 | 30 min | E | Codasip’s Next-Generation Processor Architecture Technology (tentative title) | TBD | Codasip | – |
10:25-11:05 | 30 min | E | Booth exhibition starts | ||
11:05-11:35 | 30 min | E | “Utilizing RISC-V to Powerfully Support the Future of AI and Automotive by AndesAIRE” (tentative title) | Charlie Hong-Men Su | Andes Technology | – |
11:40-12:00 | 15 min | E | Poster Session Introduction | Hironori Nakajo | Professor, Department of Intelligent Information Systems Engineering, Tokyo University of Agriculture and Technology (Japan) | – |
12:00-15:00 | 180 min | E | Poster presentation at the south foyer of Ito Hall, B2 | Poster Presenters | – |
12:00-15:30 | 210 min | – | Luncheon (Special Session: Japan’s Semiconductor Strategy 2025) | Lunch Served | – |
12:50-13:00 | 10 min | JE | “Japan’s Semiconductor Strategy 2025” – Fab Use Cases | Haruyuki Tago | Editor of “Reading Japan’s Semiconductor Strategy 2024” | |
13:05-13:25 | 10 min | J | METI on semi HR development, adv. fab use case | Hisashi Saito | Deputy Director, IT industry division, Commerce and Information Policy Bureau, Ministry Economy, Trade and Industry | |
13:30-13:40 | 10 min | J | LSTC: The Technology Research Association of Leading-Edge Semiconductor Technology Center | Masahiko Mori | Managing Director | Leading Edge Semiconductor Technology Center (LSTC) | |
13:45-13:55 | 10 min | J | Automotive ASRA:自動車用先端 SoC 技術研究組合の取り組み | TBD | ASRA:自動車用先端 SoC 技術研究組合 | |
14:00-14:10 | 10 min | J | Advancing Semiconductor Education: VDEC’s Role in Nurturing Tomorrow’s Engineers | Makoto Ikeda | VDEC (VLSI Design and Education Center), University of Tokyo | |
14:15-14:25 | 10 min | J | Tenstorrent’s Initiatives in RISC-V AI in Japan | TBD | Tenstorrent | |
14:30-14:40 | 10 min | J | Andean IP Support for Japan’s Advanced Semiconductor Supply Chain | Frankwell Jyh-Ming Lin | Andes Technology | |
14:45-14:55 | 10 min | JE | Summary | Haruyuki Tago | Editor of “Reading Japan’s Semiconductor Strategy 2024” | |
12:00-15:00 | 210 min | – | Luncheon (including special session: Japan’s Semiconductor Strategy 2024) Ends |
| |
14:40-14:55 | 20 min | E | Poster Session Winners Announcement | Hironori Nakajo | Professor, Department of Intelligent Information Systems Engineering, Tokyo University of Agriculture and Technology (Japan) | |
15:00-15:20 | 20 min | J | Lauterbach product description | TBD | Lauterbach Japan | |
15:25-15:45 | 20 min | J | Verisiliocon Japan | Nob Moriwaki | VP of Sales, Japan | Verisilicon Japan | |
15:50-16:10 | 20 min | J | Arranged RISC-V Flash MCU「R9A02G021」TBD | TBD | ルネサス株式会社 | – |
16:10-16:35 | 30 min | J | Arranged Automotive RISC-V「自動車の電子化と自律化について」(仮題 | TBD | デンソー | – |
16:40-17:00 | 20 min | E | Ventana Microsystems Out-of-Order RISC-V for Data Centers | Travis Lanier | Ventana Microsystems | |
17:05-17:35 | 30 min | J |
| TBD | Rapidus K.K. | – |
17:40-17:50 | 15 min | JE | Summary | Haruyuki Tago | Editor of “Reading Japan’s Semiconductor Strategy 2024” |
|
17:50-18:00 | 15 min | – | Dismantling | Dismantling | – |
④ RISC-V RISC-V Technology Exhibition
August 1, 2024 10:00-15:30
B2F Foyer, multipurpose space
Please note that exhibitors and content are subject to change.
ブース番号 | Time | Booth Title (with URL) | Company (with URL) | Note |
---|---|---|---|---|
A | 10:00-15:00 | Andes Technology | Andes Technology | |
B | 10:00-15:00 | Codasip | Codasip | |
D | 10:00-15:00 | TBD | TBD | |
E | 10:00-15:00 | TBD | TBD | |
F | 10:00-15:00 | Tentorrent AI Products | Tenstorrent | |
G | 10:00-15:00 | TBD | TBD |
ブース番号 | Time | Booth Title (with URL) | Company (with URL) | Note |
---|---|---|---|---|
1 | 10:00-15:00 | TBD | TBD | |
2 | 10:00-15:00 | eFabless / OpenMPW chip / TinyTapeout Metallurgical microscope projection of chip, Kyushu Institute of Technology chip, OpenMPW8 inch wafer, inverter puzzle, etc. | ISHI-KAI | |
3 | 10:00-15:00 | TBD | TBD | |
4 | 10:00-15:00 | DTS Insight’s RISC-V ICE Solution | DTS Insight | |
5 | 10:00-15:00 | TBD | TBD | |
6 | 10:00-15:00 | VeriSilicon IP Solutions and Services | VeriSilicon K.K. | |
7 | 10:00-15:00 | RISC-V Fedora Linux with Compilers, Runtimes, and Emulators | Red Hat China and PLCT Lab (Programming Languages and Compilation Technologies Lab) | |
8 | 10:00-15:00 | TBD | TBD | |
9 | 10:00-15:00 | JASA Chip Demo | Masataka Kobayashi | Japan Embedded Systems Technology Association (JASA) Technology Headquarters Hardware Committee RISC-V Working Group (Hitachi Industry & Control Solutions, Ltd.) | |
10 | 10:00-15:00 | RISC-V Processor IP Security Demo | University of Electro Communication | |
11 | 10:00-15:00 | TBD | TBD |
⑤ RISC-V research and open semiconductors
August 1, 2024 13:00-
Moderator: DTS Insight Co., Ltd.
Product Solutions Division
Sales Department, Sales Division 1
Kuriya Atsushi
The lecture name, lecture content and time are provisional and subject to change depending on the situation.
Time | Duration in Min | Language | Presentation Title | Presenter | Affiliation (click for details) | Materials |
---|---|---|---|---|---|
13:00-13:30 | 30 | – | JASA RISC-V Chip Project | Tomohisa Kohiyama (Hitachi Industrial Equipment Systems Co., Ltd.) | Technical Headquarters Hardware Committee RISC-V Working Group Chief, Embedded Systems Technology Association (JASA) | |
9:30-9:45 | 10 | E | Master of Ceremony’s Words of Welcome | Haruyuki Tago | SH Consulting K.K. | – |
9:50-10:10 | 20 | – | Opening Lecture: Japan’s Semiconductor Strategy | Ministry of Economy, Trade and Industry, Information and Communication Industry Division業課・課長補佐 | – |
10:10-10:20 | 10 | – | 10 Minute Reseating | Bio Break | – | – |
10:20-10:50 | 30 | – | Presentation 11 | TBD | – |
17:40-17:50 | 10分 | 日 | Closing Remarks | TBD | – |
17:50-18:00 | 10分 | – | Cleanups | – | – |
⑥ AI, RISC-V research poster presentation
August 1, 2024 10:30-15:30
B2F Foyer
Technology exhibition location: Location No. Please refer to the layout diagram for RISC-V poster exhibition (Foyer).
技術展示場所 :Location No. RISC-V ポスター 展示 (ホワイエ)の配置図を参照ください。
枠 | 発表時間 | 言語 | 出展テーマ | 発表者 | 所属機関 | ポスター | |
---|---|---|---|---|---|---|
P1 | 10:30-15:30 | Poster Presentation 61 | TBD | – | ||
P2 | 10:30-15:30 | Poster Presentation 62 | TBD | – | ||
P3 | 10:30-15:30 | Poster Presentation 63 | TBD | – | ||
P4 | 10:30-15:30 | Poster Presentation 64 | TBD | – | ||
P5 | 10:30-15:30 | Poster Presentation 65 | TBD | – | ||
P6 | 10:30-15:30 | Poster Presentation 66 | TBD | – | ||
P7 | 10:30-15:30 | Poster Presentation 67 | TBD | – | ||
P8 | 10:30-15:30 | Poster Presentation 68 | TBD | – | ||
P9 | 10:30-15:30 | Poster Presentation 69 | TBD | – | ||
P10 | 10:30-15:30 | Poster Presentation 610 | TBD |
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⑦ RISC-V Press Business Card Exchange (Invitation Only)
August 1, 2024 12:00-13:00
Moderator: DTS Insight Co., Ltd.
Product Solutions Division
Sales Department, Sales Division 1
Kuriya Atsushi (scheduled)
時間 | 発表時間 | 言語 | プレゼンテーション題名 | 発表者 | 所属機関 | Note | |
---|---|---|---|---|---|---|
12:00 | J | 開場 | – | |||
12:10-12:15 | J | 歓迎の挨拶 | TBD | — | ||
12:15-12:55 | J | 歓談 | TBD | |||
12:55-13:00 | J | 閉会 | – |
⑧ RISC-V related Japanese publications
Click on the book photo to purchase
Digital Circuit Design and Computer Architecture [RISC-V Edition] (00) Large book – June 7, 2022
Computer Architecture [6th Edition] Quantitative Approach Paperback – 2019/9/25 ¥8,800
Learning RISC-V and Chisel: Building your own CPU for the first time – The first step towards implementing a custom CPU using an open source instruction set Paperback (soft cover) – 2021/8/25 ¥3,520
A must-read book for those who want to start Chisel Paperback – August 28, 2020 ¥2,750
Getting Started with FPGA Electronics with Chisel Paperback – 2022/1/9 ¥2,750
RISC-V related Japanese publications