Put RISC-V into Your Computer Architecture Course Using RVfpga!

RVfpga: Understanding Computer Architecture In-person Workshop 7th and 8th, March ’23

Workshop introduction and Registration page

7th March: https://www.eventbrite.co.uk/e/445258248407

8th March: https://www.eventbrite.co.uk/e/479969651147

Location: Yagami Forum, 7th Floor, Building 14, Yagami campus, Keio University

3 Chome-14-1 Hiyoshi, Kohoku Ward Yokohama, Kanagawa, 223-8522　Japan

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By: Robert Owen               2023-4th-Jan.

Dear Professors and Friends,

Online is convenient and has saved us during the pandemic, but you can’t beat in-person, in-class! That immersive feeling of hands-on and the shared mission with colleagues all trying to master the same subject.

We are in the middle of a global series of workshops to “train the teachers” on how to use RISC-V in computer architecture courses and the design of systems on chip (SoCs). We started in the USA last year, and fitted in several Europea events as well. Of particular note is the December Workshop in Silicon Valley attended by nearly 60 Teachers and Trainers! 

Now we are heading East: to Israel, Japan, Taiwan, Korea and China.

RVfpga partners, including Digi-Key, are working with us to make this possible!

To do this, we are asking for a day of your time so that you can empower the next generation of computer science and engineering students to get real-world expertise in computer architecture and the RISC-V instruction set architecture.

What is RVfpga?

This in-person, one-day RVfpga workshop presents a commercial RISC-V system targeted to an FPGA, discusses the theory, architecture, and course structure, and shows how to use the hands-on labs as part of the complete RVfpga course. The course explores the fundamentals of computer architecture using Western Digital’s open-source, fully verified, already in-silicon, SweRV EH1 RISC-V core targeted to a Xilinx Artix 7 FPGA on Digilent’s Nexys A7 development board. Everyone will get hands-on experience with the FPGA platform and the software tools, enabling a fast start when you return to your university.

The SweRV is not an “education core”. It’s real-world, used inside Imagination’s GPUs and Western Digital’s solid-state drives.

What will you learn?

• The workshop shows how to quickly get the RISC-V FPGA system and RISC-V tools up and running
• We describe each of the labs and work through a selection of them hands-on
• We will also discuss how to integrate RVfpga into your curriculum

Specific topics include:

• Installing the tools (which we encourage before the workshop)
• Targeting the SweRV EH1 RISC-V core and SoC to an FPGA
• Programming the RISC-V SoC
• Adding more functionality to the RISC-V SoC
• Analyzing and modifying the RISC-V-core and memory hierarchy

Who should attend?

• It’s primarily a “Train the Teacher” event, of greatest value to EE, CS, and CE Teachers who want to teach Computer Architecture
• Trainers in commercial companies, start-ups evaluating RISC-V, and postgrads considering a career in teaching or becoming a chip designer will also find it useful

Networking

It’s a great opportunity to make new and refresh existing links with fellow Professors who are keen to keep their courses up-to-date. Help us spread the word and bring your colleagues.

Meet innovators who are evaluating RISC-V for start-up projects, and company trainers who need great materials to train new recruits.

Our Trainers:

By teaming-up with skilled academics, and experts in other companies working on RISC-V, we are blessed with some of the most expert instructors in the world !

– Israel

Itai Yarom has long experience of CPU architecture, working for companies like Intel, Imagination, MIPS and Synopsys. Itai was a teaching professor at the Hebrew University, instructing courses on computer architecture and others, and also guided engineering student projects collaborating with the industry (for example, Cadence’s Conformal ECO tool is an example of a students project that became an EDA tool). Itai has an M.Sc. in computer science, with a focus on AI, Machine Learning and Multi-Agent Systems, with particular interest in system self recovery and repair. Itai developed over 20 silicon products, wrote more than 20 papers and holds several patents and awards.

Our local host in Israel is Lab Manager Jacob Fainguelernt, well known to an entire generation of Israeli graduates who completed their projects under his guidance.

– Japan & Taiwan

Michio Abe, established expert on RISC CPU Architectures. He is Director, Sales & Solution, Japan, at MIPS LLC. 

His career started at NEC in 1985, and he has been involved in the development of MIPS CPUs including the development of the original NEC’s MIPS CPUs in 1991. This was followed by developing in-vehicle SoCs with MIPS and other cores and architectures. He has been in charge of promotion and marketing of MIPS CPU in Japan since 2015, initially as part of Imagination Technologies and now as a stand-alone company.

Our local host is Prof. Hideharu Amano from Keio University. He is well known internationally as an expert in Computer Architecture and a leading researcher on this topic.

Dates

Each workshop runs for one day, and may have a repeat the following day if there is sufficient demand.  

Workshop Series (date & location)

More information

• About the IUP and RVfpga: https://university.imgtec.com/teaching-download/
• RISC-V blog: https://blog.imaginationtech.com/how-rvfpga-understanding-computer-architecture-will-give-under-grads-real-world-skills
• Intro to RISC-V: https://www.digikey.com/en/resources/risc-v

We look forward to meeting you in person!

Best Regards,

Robert C.W. Owen

Principal Consultant: Worldwide University Programme

Web: www.imgtec.com/university 

Twitter: @UniPgm

www.imaginationtech.com

About this author

Robert Owen created and directed three of the world’s leading industry-to-university programs for Texas Instruments (“TI”), Imagination Technologies, and RS Components (in Europe & Asia).

In parallel, he created and ran a successful media business.

In 2019 he returned to Imagination to revive and reposition the Imagination University Programme, the “IUP”, which is now focused on the “silicon engines” of GPUs (Graphics Processors), NNAs (Neural Network Accelerators), and new developments of a RISC-V-based family of CPUs. The application of these processor engines is driving strong needs for new education projects with a particular emphasis required for hands-on learning using industrially-proven technologies.

These projects enable teachers of the next generation of engineers and programmers to understand how to solve real-world problems with these exciting technologies.

Now in his 29th year in the field of Industry-to-Academia collaboration, Robert has unique insight into this market and a formidable network of relationships around the world.

In 2022 Robert is working with Digi-Key’s Academic Program to bring world-class labs and classes based on RISC-V processors to universities globally.