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RISC-V Days Tokyo 2022 Autumn Online RISC-V Pavilion

 


 

ImperasDV for RISC-V processor functional design verification Demo PDF Demo Video

Booth Attendant:
Shuzo Tanaka
VP & Director
Engineering Department
eSOL Trinity Co., Ltd.

Imperas is the leader in RISC-V simulation solutions. For RISC-V processor DV the ‘lock-step-compare’ methodology verifies the core RTL against a high-quality reference including asynchronous events and debug operations.

ImperasDV natively supports the open standard RVVI (RISC-V Verification Interface) that covers the RISC-V ISA (Instruction Set Architecture) including privileged mode, vector accelerators, multi hart, multi-cores, as well as custom extensions.

The Imperas RISC-V Reference model can be encapsulated within a UVM test bench and SystemVerilog environment to give a unified debug experience across the RTL and Reference model to enable efficient issue resolution when a discrepancy is found.

 


 

Marmot System with PSU and Solar power supply Demo PDF YouTube Demo Video

Booth Attendant:
Hoan Huynh
Senior Software Engineer, SH Consulting Vietnam Company Limited



Figure 1: Full Diagram of a RISC-V AWS IoT Core Device Example

This demonstration shows a capacity of PSU (Power Supply Unit) for manage power for Marmot System by using Solar panel and battery. By monitor voltage on the Solar and Battery, PSU can decide resource of power supply will be use. In the case good sunshine, PSU use power from Solar to (1) Keep the system work as normal (2) Can charge for battery. Otherwise PSU can use power from battery.

 


 

About RISC-V Association

RISC-V-logo-figonly-mod-2

RISC-V Association is an association among RISC-V Foundation member companies. RISC-V Foundation defines Member Sponsored Events and Meetups as regional efforts and RISC-V Association supports these events. Presently Software Hardware Consulting handles business ends of this activity.

Recent Posts

  • The calm before the storm: Images from around noon June 20 on the day RISC-V Day was held.
  • The RISC-V Day Summer event on June 20 had 450 participants, making it the largest ever!
  • RISC-V Day secretariat will offer gift book “Google Semiconductors, RISC-V, and World Electronic Geopolitics,” which outlines the U.S. Department of Defense soft semiconductor strategy in Asia, to attendees of “RISC-V Days Tokyo 2023 Summer” on June 20th.
  • Call for Posters for Poster Session at RISC-V Day Tokyo 2023 Summer Deadline Extended until June 12
  • Part Time Event Work June 10 and June 20, 2023
  • Call for Posters for Poster Session at RISC-V Day Tokyo 2023 Summer (New)
  • The scale of RISC-V’s IP license business is approaching that of the UK’s ARM after eight years of being public! The program content for “RISC-V Days Tokyo 2023 Summer,” which will be held at the Hongo Todai Ito Memorial Hall in Bunkyo Ward on June 20, has been released.
  • Tenstorrent is a Platinum Sponsor of RISC-V Day on June 20, 2023
  • Call for Proposal draft of poster session for RISC-V Day Tokyo 2023 Summer released.
  • On June 20, 2023, the RISC-V Alliance Japan will sponsor Japan’s largest RISC-V conference, “RISC-V Day Tokyo 2023 Summer.” A trade show and poster session will also be held at the same time.

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