Accelerate Silicon Research with Google Cloud Platform

Booth Attendant:
Johan Euphrosine

Google, Developer Relations Engineer

Between each batch of experiments we reported the estimated total power consumption to the Vertex AI Vizier service, allowing it to suggest new parameters that quickly converge toward the best power metrics for this design.

D: PL_TARGET_DENSITY
A: DIE_AREA^mm2
P: TOTAL_POWER

Comprehensive Solutions for RISC-V Architecture form Siemens EDA

Booth 

Booth Attendant:

Yuri Ellison | Marketing Program Manager, Siemens EDA (Japan)

Siemens EDA offers comprehensive RISC-V solutions including RISC-V integrity verification solution that apply formal verification methodology, DFT solution for silicon debugging and bring-up, and high-level design solution rationing for shift-left in the design cycle, as well as RTOS, middle-ware, IP, tools, and services to enable jump-starting embedded system development.

Imperas RISC-V virtual prototype booting Zephyr OS and running applications.

Booth Attendant:
Shuzo Tanaka
VP & Director
Engineering Department
eSOL Trinity Co., Ltd.

Imperas is the leader in RISC-V simulation solutions. For RISC-V software development the Imperas technology for virtual platforms allows the development of software before hardware is available. The VAP (Verification, Analysis and Profiling) tools support the separation of running activities to show the low-level firmware, OS processes and application code. In addition, for RISC-V further optimization can be explored with the analysis of custom instructions.
The Imperas models and technology is used to support the Japanese government projects “TRASIO” and “RVSPF” project and a demonstration will be shown with the RISC-V platform booting Zephyr OS and running applications.

ImperasDV for RISC-V processor hardware design verification.

Imperas is the leader in RISC-V simulation solutions. For RISC-V processor DV the ‘step-and-compare’ methodology verifies the core RTL against a high-quality reference including asynchronous events and debug operations.
ImperasDV also supports the open standard RVVI (RISC-V Verification Interface) that covers the RISC-V ISA (Instruction Set Architecture) including privileged mode, vector accelerators, multi hart, multi-cores, as well as custom extensions.
The Imperas RISC-V Reference model can be encapsulated within a UVM test bench and SystemVerilog environment to give a unified debug experience across the RTL and Reference model to enable efficient issue resolution when a discrepancy is found.

RISC-V custom instruction addition using Codasip Studio

Trion / Titanium FPGAs Live Demo

(Trion / Titanium FPGA ライブデモ)

Runs the Efinix Sapphire RISC-V and UNO Labo. 1-stage RISC-V on a Trion FPGA to display biometric information and power consumption.

Titanium FPGA will be conducting real-time image processing and real-time AI object tracking demos.

Booth Attendant:
Hoan Huynh
Senior Software Engineer, SH Consulting Vietnam Company Limited

This demonstration shows a full integration of secure OTA firmware upgrade and digital caliper monitor for an IoT with a 32-bit RISC-V running FreeRTOS on Marmot System. In this demonstration the RISC-V RTOS-based IoT conducts OTA via LTE Mobile SIM leveraging Amazon Web Services (AWS) IoT Core.
Output data from digital caliper is sent to AWS IoT, User can check the data by using PC or Mobile device browser to web app.