時間
写真

発表題目
発表概要

発表者
経歴

13:10-13:30

Welcome Remarks
Makoto Ikeda, representing the University of Tokyo, addresses the critical shift in the semiconductor landscape where RISC-V has evolved from an academic standard into a vital industrial pillar. His remarks focus on the “democratization” of chip design, highlighting how open-standard architectures enable Japanese industry and academia to co-innovate in high-growth areas like AI, robotics, and automotive systems.

Makoto Ikeda | Professor at the University of Tokyo
Dr. Ikeda is Special Advisor to the President of the University of Tokyo and Director of d.lab at the University of Tokyo. He also serves as Science Adviser to Japan’s Ministry of Education, Culture, Sports, Science and Technology (MEXT), contributing to national policy in science, technology, and advanced research strategy.

A Professor at the University of Tokyo since 2013, he previously served as Associate Professor, Lecturer, and Research Associate, building a distinguished academic career spanning nearly three decades at Japan’s leading research university. His work bridges advanced semiconductor technology, integrated circuit design, and system-level innovation, with a strong emphasis on translating fundamental research into practical societal impact.

13:30-14:00

Standard Cell Library Development and Design Infrastructure Establishment for the 2nm Process at Rapidus — Powered by Raads
　Standard cells are small fundamental circuits composed of a single logic gate or up to a dozen gates. Only when a library containing several hundred types of such cells is properly prepared can full SoC design be realized. A complete cell library must include the various models and views required by EDA tools, such as electrical characteristic models, HDL models for logic simulation, and physical views including LEF/DEF and GDS-II for place-and-route.
　At Rapidus, within the Raads (Rapidus AI-Assisted Design Solutions) design environment, standard cell library development is a foundational element of the 2nm design infrastructure. While user-facing production libraries are outsourced to a third party (Synopsys), Rapidus also develops in-house libraries to support internal evaluation, validation, and benchmarking of external libraries. (Note: Presentation title and abstract prepared by the organizer.)

Koki Tsurusaki | Director, Design Technology Division, Engineering Center, Rapidus Corporation
 Koki Tsurusaki was involved in semiconductor physical design and floorplanning technology development at Renesas Electronics and is listed as an inventor on patents related to design optimization methodologies. He currently serves as Director of the Design Technology Division at Rapidus Corporation, where he leads the development of the AI-enabled design environment “Raads” and the establishment of design infrastructure for advanced process technologies.

14:00-14:30

Open Silicon for the AI Era: Tenstorrent and AI Everywhere
 As the business environment is rapidly transforming with the rise of AI, strengthening Japan’s market competitiveness has become an urgent priority. This requires advances not only in semiconductor manufacturing, but also in key chips, software, and human resource development.This talk introduces Tenstorrent’s open and advanced technology solutions and their role in building a competitive AI and semiconductor ecosystem.

Mamoru Nakano, APAC Region Manager & Japan Country Manager at Tenstorrent
Since the company’s establishment in January 2023, he has been leading its business expansion and organizational development in the Japanese market. Prior to joining Tenstorrent, he served as Country Manager of Graphcore Japan, overseeing sales, marketing, and customer engagement. Before that, he spent approximately 16 years as President and Representative Director of Cray Inc. Japan, driving the HPC business and supporting growth across the Asia region. Earlier in his career at HP, he held the role of General Manager for HPC and Linux business across Asia, building a long-standing track record at the forefront of high-performance computing and cloud infrastructure.

14:30-15:00

SiFive 2nd Generation Intelligence Family Introduction
 This talk presents the second generation of the SiFive Intelligence Family, a suite of RISC-V-based AI accelerator IP cores. These cores support efficient edge AI acceleration across applications from low-power far-edge devices to cloud-scale systems. Built on the open RISC-V standard with custom extensions, the family ensures compatibility with the RVA23 profile, enabling seamless integration with custom accelerators for AI inference, large language models, and related workloads.

Yoshihito Kondo | Representative Director, SiFive Japan
 Yoshito Kondo is a semiconductor industry leader serving as Representative Director of SiFive Japan, the Japanese subsidiary of U.S.-based SiFive. He joined Sony Corporation in 1990, where he was engaged in the development of system LSIs, including media processors. In 2019, he moved to DTS Insight Corporation, where he was involved in SiFive’s distribution and technical support activities in the Japanese market. He joined SiFive Japan in October 2022, initially overseeing technical support including field application engineering, and later assumed leadership of the company, driving the adoption and business expansion of RISC-V processors.

15:00-15:30
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Software Guided Intelligence for Physical AI Platform Design with RISC-V
　In this presentation, Takuya Katayama will show how the change from hardware-first to software-first platform architecture is driving changes for embedded design. With RISC-V and the power of virtual models, it is now possible to start with the workload, select and optimize the hardware, and finalize the platform without time-consuming, budget-busting tape-out cycles. The appearance of software-guided intelligence is enabling changes in design methodology that deliver faster time to market, lower total cost of development, and more efficient edge silicon. This is supported by the open, modular and extensible nature of RISC-V instruction set architecture for building workload-focused instructions and extensions.

Takuya Katayama, MIPS Technical Marketing for Software & Tools
Mr. Katayama is regarded as a business leader in the semiconductor industry who is involved in the product management domain at MIPS. Within the company’s processor and platform ecosystem, built around its RISC architecture IP, he plays a role related to software and tools strategy. He is engaged in activities that bridge technology and market needs in the embedded and semiconductor sectors.

15:30-16:00

Powering the Future of Compute with Andes RISC-V
　The future of computing is being dramatically transformed by open and scalable architectures. Evolution in the fields of AI, edge, and cloud requires flexible and optimizable designs, and RISC-V is a core technology for this.
In this presentation, Frankwell Lin, CEO of Andes Technology, will introduce the latest trends and strategies for RISC-V, which is being put into practical use at the commercial level. He will explain how customers can develop differentiated products more quickly through high-performance, low-power processor IP, vector extensions, and a powerful software ecosystem.

Frankwell Lin, Chairman & CEO of Andes Technology (Taiwan)
　Frankwell Lin, Chairman of Andes Technology, started his career being as application engineer in United Microelectronics Corporation (UMC) while UMC was an IDM with its own chip products, he experienced engineering, product planning, sales, and marketing jobs with various product lines in UMC. In 1995, after four years working on CPU chip product line as business director, he was transferred to UMC-Europe branch office to be its GM when UMC reshaped to do wafer foundry service, he lead UMC-Europe to migrate itself
from selling IDM products to selling wafer foundry service. In 1998, after 14 years working in UMC, Frankwell switched job to work in Faraday Technology Corporation (Faraday), he lead ASIC business development as starting, then on-and-off leading ASIC implementation, chip backend service, IP business development, industry relationship development (IR), as well as Faraday's spokesperson, in 2004, he started to lead the CPU project spin off operation of Faraday. Frankwell became co-founder of Andes Technology Corporation in
2005 when it was found up, he formally took position to be Andes' President since 2006 and got promoted as Chairman and CEO in 2021.
 Frankwell received BSEE degree of Electrophysics from the National Chiao-Tung University, Taiwan, and MSEE degree of Electrical and Computer Engineering from Portland State University, Oregon, USA. Under his management, Andes has been recognized as one of leading suppliers of embedded CPU IP in semiconductor industry. Andes also won the reputation of leading technology company with awards such like 2012 EE Times worldwide Silicon 60 Hot Startups to Watch, 2015 the Deloitte Technology Fast 500 Asia Pacific award, etc. Frankwell received accolade award of Outstanding Technology Management Performance, Taiwan, in 2015 and ERSO award in 2020 for his contribution to the high-tech industry. Frankwell is the Board Director of RISC-V International since 2020. Frankwell was also
elected to be the Chairman of RISC-V Taiwan Alliance (RVTA) since 2023.

16:00-16:20

A Case Study of Custom AI Accelerator Development Using RISC-V
This article uses actual examples to introduce the role RISC-V has played in developing a custom AI accelerator for FPGAs at Future, as well as the flexibility of customization made possible by RISC-V’s open architecture.

Yuki Miyashita | Future Corporation ki-labs | FPGA Lead
At a general electric manufacturer, he worked on FPGA development for autonomous driving and medical equipment, pursuing system design with high reliability, low latency, and real-time processing. Leveraging his expertise, he is currently a member of Future Corporation’s in-house R&D organization, “ki-labs,” where he leads the design and development of hardware acceleration as an FPGA lead.
Shu Kitamoto | Future Corporation ki-labs | Software Engineer
After working on business systems development at an SIer, he is now a member of Future Corporation’s “ki-labs.” As a software engineer, he is responsible for implementing the processor instruction issuing layer. He pursues faster AI inference by optimizing the boundary between higher-level software and hardware. His hobby is competitive programming (AtCoder Blue).
Ryuji Fuchikami | Future Corporation ki-labs | Architect
Graduated from Kyushu Institute of Technology in 1999. He has worked in the research and development department of a major electronics manufacturer for over 20 years, establishing image sensing and ultra-high-speed, low-latency real-time signal processing technologies. He specializes in the boundary between hardware and software, and has pursued optimization technologies that utilize the characteristics of computer architecture, including the invention of the deep learning model “LUT-Network” for FPGAs. He has written numerous articles, including in “Interface” (CQ Publishing). He is currently working at ki-labs, Future Inc., designing AI accelerator architectures.

16:20-16:40

TRACE32: Advanced Debug and Trace Solutions for RISC-V
 RISC-V adoption is rapidly expanding across a wide range of domains, from embedded devices to high-performance SoCs. As systems become increasingly complex through multi-core integration and heterogeneous architectures, the importance of advanced development and analysis environments continues to grow.
 This talk introduces the latest trends in high-end debug and trace technologies for RISC-V systems. It explains how TRACE32’s comprehensive debug solutions—such as non-intrusive observation and synchronized multi-core debugging—can contribute to efficient analysis and resolution of complex system-level issues.

Yuji Mori | Representative Director, Lauterbach Japan Co., Ltd. (Germany)
　Yuji Mori serves as Representative Director of Lauterbach Japan Co., Ltd., the Japanese subsidiary of Germany-based Lauterbach, a global leader in debug and trace solutions for embedded systems. Over the course of his career, he has been involved in development and technical support within Japan’s major semiconductor and embedded industries, including companies such as Hitachi and Renesas Electronics, building extensive experience in SoC and embedded system design and debugging. At Lauterbach, Mori oversees business development and customer engagement in the Japanese market, promoting more efficient development for increasingly complex next-generation systems such as multi-core SoCs and RISC-V platforms through advanced technologies including non-intrusive tracing and synchronized multi-core debugging.

16:40-17:00
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Debugging Environments Supporting RISC-V Development: Tools and Practical Challenges in Real Hardware Development
 This session addresses common challenges encountered in RISC-V software development—such as initial boot bring-up, RTOS debugging, and trace analysis—and introduces practical development and verification methodologies using ICE.
 As RISC-V adoption accelerates across industrial applications, the most critical requirement for development teams is an environment that enables efficient bring-up and in-depth analysis on real hardware. DTS INSIGHT provides embedded developers with robust debug and trace environments through its RISC-V–compatible ICE (In-Circuit Emulator) products.

Tetsuo Asada | DTS Insight Corporation (Japan)
　After joining DTS Insight Corporation (formerly Yokogawa Digital Computer Corporation), he worked on the development of the debugger microVIEW-PLUS. He later engaged in customer support and subsequently contributed to the development of the dynamic analysis tool TRQer. He is currently responsible for the development of adviceXross.
　For many years, he has been involved in both the development and support of embedded development support tools, gaining deep expertise in the debugging mechanisms provided by CPU architectures. Leveraging this experience, he is engaged in the development of debugging and dynamic analysis tools.

17:00-17:10

Closing Remarks: Leveraging RISC-V to Revitalize Japan’s Digital Sector
 Japan’s digital sector is highly dependent on overseas sources for cloud infrastructure, AI computing resources, and core server technologies, and the import structure of data center technology is restricting industrial competitiveness and digital sovereignty. RISC-V represents one of the few strategic opportunities to bring standardization and implementation capabilities domestically through an open ecosystem, and could become an important pillar for rebuilding the semiconductor and digital industrial infrastructure.
 In closing, I would like to reorganize today’s discussion as the intersection of policy, standardization, implementation, and human resource development, and confirm that industry, government, and academia working together to establish the RISC-V ecosystem in Japan is essential for revitalizing Japan’s digital sector and establishing next-generation industrial competitiveness.

Takuhiro Nakajo | Associate Professor, Institute of Engineering, Graduate School of Tokyo University of Agriculture and Technology
 Takuhiro Nakajo graduated from the Department of Electrical Engineering, Faculty of Engineering, Kobe University in 1985, and received his Master’s degree in Electronic Engineering from the Graduate School of Engineering at Kobe University in 1987. Since 1999, he has served as an Associate Professor in the Division of Advanced Information Technology and Computer Science, Institute of Engineering, Graduate School of Tokyo University of Agriculture and Technology.
 His research areas include processor architecture, embedded systems, and reconfigurable computing, and he has been engaged for many years in research aimed at advancing computer systems.
 In addition to his research activities, he is widely known for his significant contributions to computer science education in Japan. He has served as a co-translator of the Japanese editions of the internationally renowned textbook Computer Architecture: A Quantitative Approach by John L. Hennessy and David A. Patterson (commonly known in Japan as “HenePata”), from the 4th through the 6th editions, as well as Digital Design and Computer Architecture by David Money Harris and others (including the 1st edition, ARM edition, and 2nd edition). Through these translations, he has helped disseminate modern architectural theory in Japan.
 He is a member of the Information Processing Society of Japan (IPSJ), the Institute of Electronics, Information and Communication Engineers (IEICE), the IEEE Computer Society, and ACM, and holds a Ph.D. in Engineering.