Presentation Title
Abstract

Presenter
Bio

Main Hall
10:00-10:20

Invited Talk: Current Status and Future Policy Directions of Japan’s Semiconductor and Digital Industry Strategy
The Ministry of Economy, Trade and Industry (METI) formulated the “Semiconductor and Digital Industry Strategy” in 2021. Since then, METI has continued to convene the Semiconductor and Digital Industry Strategy Study Group on an ongoing basis. In this talk, based on the latest version of the Semiconductor and Digital Industry Strategy, we will provide an overview of the concrete strategies and initiatives, with a particular focus on semiconductor-related measures.

Hisashi Saito | Ph.D. (Engineering) , Deputy Director / Senior Coordinator | Information Industry Division, Commerce and Information Policy Bureau, Ministry of Economy, Trade and Industry (METI)
Hisashi is committed to revitalizing Japan’s semiconductor and electronics industries through integrated promotion of technology development and industrial policy. After spending around ten years in private-sector semiconductor R&D with strong experience in manufacturing and process technology, he joined the Ministry of Economy, Trade and Industry (METI) in 2021. Since then, he has played a key role in shaping Japan’s semiconductor strategy, supporting technology development, and attracting manufacturing investment.

Main Hall
10:30-11:00

Invited Talk: Current Status of the “RISC-V Server SoC Specification”
 In recent years, data center and server systems have been required to meet a wide range of platform-level demands, including Reliability, Availability, Serviceability (RAS), security, guaranteed performance, and long-term maintainability.
 This talk provides an overview of the concept of a standardized server platform foundation that enables RISC-V to expand into the data center–scale server market, and explains its technical significance.
 The primary goal of the RISC-V Server SoC Specification is to allow OS and hypervisor vendors to boot and run a single binary OS image on RISC-V servers without modification. In other words, the specification seeks to standardize hardware interfaces and functional requirements in areas where differentiation or vendor-specific implementation should not be necessary, thereby improving software compatibility and portability across RISC-V server platforms.
 This specification is positioned as one component of a broader server platform standard. When combined with essential elements such as UEFI/ACPI-based boot and runtime services, security models, platform firmware, and management mechanisms including BMC, it forms the basis of a complete RISC-V server platform standard.
 The presentation will cover: (a) Clock, timer, and interrupt control, (2) DMA protection and virtualization support through the RISC-V IOMMU, (3) PCIe subsystem integration rules, (4) Standardized RAS error record formats, (5) Mitigation of noisy-neighbor effects through QoS guarantees, (6) Industry-standard APIs for remote AI server management such as Redfish, (7) Common server management specifications including PLDM (Platform Level Data Model), (8) Management communication protocols such as MCTP (Management Component Transport Protocol). Through these topics, the talk highlights the essential building blocks required for robust and interoperable RISC-V server infrastructure. (Title and abstract prepared by the organizers.)

Vedvyas Shanbhogue | Semiconductor Engineer | Meta (formerly Facebook) | Vice Chair, RISC-V ISA Security Horizontal Technical Committee | Chair, Confidential Computing SIG/TG (RISC-V International)
 Vedvyas (“Ved”) Shanbhogue is a semiconductor architect at Meta, where he develops compute platforms for next-generation data center infrastructure. His work spans critical domains for cloud and AI systems, including security, virtualization, power management, and new ISA extensions across both RISC-V and x86 architectures. Ved has deep expertise in hardware security technologies that enable Confidential Computing, as well as in the integration of virtualization stacks such as KVM and Xen with key platform mechanisms including PCIe Integrity and Data Encryption (IDE), IOMMU, and Intel virtualization technologies (VT-x/VT-d).
 Beginning in 2021, Ved served as a Member of Technical Staff at the RISC-V startup Rivos Inc., contributing to the development of next-generation CPUs and AI data center system foundations. Following Meta’s acquisition of Rivos in 2025, he joined Meta’s data center silicon organization. Ved spent 21 years at Intel, ultimately as a Senior Principal Engineer, where he led the design of advanced processor security mechanisms that strengthen trust and isolation, including Control-flow Enforcement Technology (CCE/CET) and Trust Domain Extensions (TDX). He also contributed to sophisticated virtualization enhancements such as VMFUNC, EPT-switching, #VE, and HLAT, as well as microarchitectural design incorporating functional safety considerations.
 Beyond hardware architecture, Ved has extensive experience in system software, including Linux and Windows driver development, microcode design for network processors, high-availability middleware for telecom infrastructure, and protocol implementations such as SS7 and GSM.
 With a full-stack perspective spanning CPU design, OS and virtualization foundations, networking, and media processing technologies (MPEG-TS, RTP, H.264), Ved is a technical leader driving the evolution of next-generation computing platforms.

Main Hall
11:00-11:30

Invited Talk: Trusted Foundations for the AI and Cloud Era — Secure Large-Scale Data Analytics with RISC-V Confidential Computing
Confidential Computing is not merely an additional security feature; it is becoming a fundamental prerequisite for entry into the next-generation data center market. By providing mechanisms for protecting data in use and enabling isolated execution environments, Confidential Computing can be realized with properly designed hardware support at an overhead of roughly 10% in computational cost.
 This talk explains the comprehensive development of Confidential Computing capabilities as a core element of the next-generation RISC-V server platform for AI cloud infrastructure. In addition to foundational technologies such as the privileged ISA, the Hypervisor Extension, the Advanced Interrupt Architecture (AIA), and the IOMMU, RISC-V is actively advancing key isolation and compartmentalization features, including the Supervisor Domains Extension and the definition of the CoVE (Confidential VM Extension) Application Binary Interface (ABI). Together, these efforts enable the realization of Trusted Execution Environment Virtual Machines (TVMs) that are isolated from both the host OS and the hypervisor.
 Furthermore, the talk introduces critical ecosystem technologies required for secure accelerator-based AI computing. These include PCIe Integrity and Data Encryption (IDE), which protects CPU–device communications (GPU/NIC/SSD) from eavesdropping and tampering, as well as protocols for mutual authentication between the host CPU and devices such as SPDM (Security Protocol and Data Model). It also covers PCIe-standard mechanisms for assigning devices securely to Confidential VMs, including TDISP (TEE Device Interface Security Protocol).
 By combining these technologies, RISC-V Confidential Computing enables the secure direct assignment of AI accelerators, remote attestation rooted in hardware Root-of-Trust, and improved interoperability through open security silicon—establishing a robust trusted foundation for large-scale AI and cloud data analytics.

Ravi Sahita | Security Engineer | Meta (formerly Facebook) | Vice Chair, RISC-V International Security Horizontal Technical Committee | Chair, Confidential Computing SIG/TG (RISC-V International)  
 Ravi Sahita is a technical leader in computer security, instruction set architectures (ISAs), open-source system software, virtualization, platform design, and distributed systems. He has extensive experience across the full lifecycle of secure system development—from research and architecture through implementation and product deployment.
 Ravi has contributed to the development of industry-standard specifications in areas such as software ABIs, security models, network security, and Quality of Service (QoS). He also has hands-on expertise with FIPS (NIST) security certification processes and has been involved in open-source virtualization implementations including Xen and KVM/Linux. He is an author of numerous technical papers and industry standards within organizations such as RISC-V International, the IETF, and the Trusted Computing Group (TCG).
 Ravi possesses deep expertise in platform security architecture spanning software, processors, chipsets, and devices. He has led data center–scale Confidential Computing initiatives, including major projects such as RISC-V CoVE, OpenTitan, and Intel TDX.
 His contributions include advanced security innovations such as ROP defense through Intel CET, defining VM introspection ISA mechanisms within Intel VT-x, implementing the first security hypervisor designed to protect guest runtime integrity (Deepsafe), and developing system defense capabilities for Intel vPro. In recent years, Ravi has also focused on protecting privacy-sensitive AI training and inference infrastructure, as well as countermeasures against adversarial machine learning. He is the holder of more than 240 patents.

Main Hall
11:40-12:10

Mamoru Nakano, APAC Region Manager & Japan Country Manager at Tenstorrent
Since the company’s establishment in January 2023, he has been leading its business expansion and organizational development in the Japanese market. Prior to joining Tenstorrent, he served as Country Manager of Graphcore Japan, overseeing sales, marketing, and customer engagement. Before that, he spent approximately 16 years as President and Representative Director of Cray Inc. Japan, driving the HPC business and supporting growth across the Asia region. Earlier in his career at HP, he held the role of General Manager for HPC and Linux business across Asia, building a long-standing track record at the forefront of high-performance computing and cloud infrastructure.

MIPS for the AI Era: Scalable Compute IP for AI, Robotics, and Edge Applications
MIPS has a long history as one of the pioneering RISC processor architectures, and in recent years has been re-established as a RISC-V–based compute IP provider. Supported by its acquisition by GlobalFoundries and a growing ecosystem of partnerships, MIPS is positioning itself to address the real-time, low-latency, and power-efficient requirements of emerging application domains such as AI inference, industrial robotics, automotive systems, and edge computingThis talk will provide an overview of how MIPS RISC-V IP can be leveraged as scalable CPU infrastructure and as a foundation for AI-enabled processing in next-generation edge systems. The session will also highlight the role of open architectures and scalable compute subsystems in meeting the evolving demands of AI-driven applications. (Title and abstract prepared by the organizers.)

MIPS, a business unit of GlobalFoundries

Main Hall
14:00-14:30

Scaling Scalar, Vector, and Matrix Computation for Modern AI Applications
 This talk presents recent advances in RISC-V computing for AI applications from SiFive’s perspective. Building on the latest progress in processor architecture and system integration, the presentation provides an overview of key technical challenges and emerging opportunities across a broad range of AI execution environments. (Title and abstract prepared by the event organizers.)

Yoshito Kondo | CEO, SiFive Japan (USA)
 Yoshito Kondo is a leader in the semiconductor industry and serves as CEO of SiFive Japan, the Japanese subsidiary of U.S.-based SiFive. He joined Sony Corporation in 1990, where he worked on the development of system LSIs, including media processors. In 2019, he moved to DTS Insight Inc., where he was also involved in SiFive’s agency business and technical support activities in the Japanese market. In October 2022, he joined SiFive Japan, initially leading technical support efforts including field application engineering. He later became the head of the company, driving the adoption of RISC-V processors and expanding SiFive’s business presence in Japan.

Application Acceleration Enabled by RISC-V Chip Design: From Architecture to Deployment
In this talk, Andes Technology will provide an overview of how system design based on its RISC-V processor IP supports application acceleration and real-world deployment. The session will also highlight the potential and future outlook of RISC-V adoption across a broad range of application domains, including 5G, artificial intelligence, data centers, smart devices, IoT, microcontrollers, and automotive and embedded systems. (Title and abstract prepared by the organizers.)

Andes Technologies Inc. 

Standard Cell Library Development and Design Infrastructure Preparation for Rapidus’ 2nm Process
Standard cells are small fundamental logic circuits composed of roughly one to a dozen logic gates. SoC design becomes possible only after a comprehensive library containing hundreds of such cells has been established. A standard cell library must include various models and views required by EDA tools, such as electrical timing models, HDL models for logic simulation, and physical design data formats including LEF/DEF and GDS-II.
For customer-facing libraries, Rapidus has outsourced development to a third party (Synopsys). At the same time, Rapidus is also building its own in-house library to support internal evaluation, process verification, and assessment of externally developed libraries. (Title and abstract prepared by the organizers.)

Hiroki Tsurusaki | Director, Design Technology Division, Engineering Center, Rapidus Corporation
Koki Tsurusaki currently serves as Director at Rapidus Corporation, where he leads efforts in digital design reference flows, design technology co-optimization, and the development of advanced design solutions for cutting-edge process technologies e.g. 2nm. Prior to joining Rapidus, Mr. Tsurusaki held key engineering positions in the EDA and semiconductor design industry, including roles such as Senior Application Engineer at Siemens EDA and as head of the Japan design center at Synapse Design Automation. At Rapidus, he has been involved in efforts to advance AI-assisted design environments such as the Rapidus AI-Assisted Design Solution (Raads), which aims to significantly reduce turnaround time in digital design flows for advanced nodes.

Main Hall
16:00-16:20 

TRACE32: Advanced Debug and Trace Solutions for RISC-V
 RISC-V adoption is rapidly expanding across a wide range of domains, from embedded devices to high-performance SoCs. As systems become increasingly complex through multi-core integration and heterogeneous architectures, the importance of advanced development and analysis environments continues to grow.
 This talk introduces the latest trends in high-end debug and trace technologies for RISC-V systems. It explains how TRACE32’s comprehensive debug solutions—such as non-intrusive observation and synchronized multi-core debugging—can contribute to efficient analysis and resolution of complex system-level issues.

Yuji Mori | Representative Director, Lauterbach Japan Co., Ltd. (Germany)
　Yuji Mori serves as Representative Director of Lauterbach Japan Co., Ltd., the Japanese subsidiary of Germany-based Lauterbach, a global leader in debug and trace solutions for embedded systems. Over the course of his career, he has been involved in development and technical support within Japan’s major semiconductor and embedded industries, including companies such as Hitachi and Renesas Electronics, building extensive experience in SoC and embedded system design and debugging. At Lauterbach, Mori oversees business development and customer engagement in the Japanese market, promoting more efficient development for increasingly complex next-generation systems such as multi-core SoCs and RISC-V platforms through advanced technologies including non-intrusive tracing and synchronized multi-core debugging.

Main Hall
16:30-16:50

TRACE32: Debug & Trace Solution for RISC-V
 RISC-V adoption is rapidly expanding across a wide range of applications, from embedded devices to high-performance SoCs. As systems become increasingly complex through multi-core architectures and advanced integration, the importance of a robust development environment continues to grow.
 In this presentation, we will introduce the latest trends in advanced debugging and trace technologies for RISC-V systems. We will explain how TRACE32 provides a comprehensive debug solution essential for analyzing complex system issues, including non-intrusive observation and synchronized multi-core debugging.

Future Corporation

Main Hall
17:00-17:20

ICE-Based Debugging Environment for RISC-V Development: Essential Tools and Real-World Challenges
 This session addresses common challenges encountered in RISC-V software development—such as initial boot bring-up, RTOS debugging, and trace analysis—and introduces practical development and verification methodologies using ICE.
 As RISC-V adoption accelerates across industrial applications, the most critical requirement for development teams is an environment that enables efficient bring-up and in-depth analysis on real hardware. DTS INSIGHT provides embedded developers with robust debug and trace environments through its RISC-V–compatible ICE (In-Circuit Emulator) products.

DTS INSIGHT Corporation

Main Hall
17:20-17:40

Closing Remarks: Revitalizing Japan’s Digital Sector through RISC-V
 Japan’s digital sector remains heavily dependent on overseas technologies in key areas such as cloud infrastructure, AI computing resources, and core server technologies. This import-driven structure surrounding data center capabilities has become a constraint on both industrial competitiveness and national digital sovereignty.
 RISC-V represents one of the few strategic opportunities through which Japan can internalize standardization and implementation capabilities via an open ecosystem. It has the potential to serve as a critical pillar in rebuilding the foundation of the semiconductor and digital industries.
 As we conclude today’s conference, I would like to reaffirm the importance of organizing the discussions we have had today at the intersection of policy, standardization, implementation, and human resource development. It is essential for industry, government, and academia to work together to firmly establish the RISC-V ecosystem in Japan, as this will be indispensable to revitalizing our digital sector and securing next-generation industrial competitiveness.

RISC-V Alliance Japan

Development of Advanced Semiconductor Design Infrastructure and Ongoing Project Plans at AIDC
This presentation introduces the current status of semiconductor design environment development at the Advanced Integrated Device Consortium (AIDC), promoted by the National Institute of Advanced Industrial Science and Technology (AIST), as well as an overview of major projects currently underway.
 At AIDC, efforts are progressing to establish a digital design environment aligned with advanced semiconductor processes, and to build an end-to-end workflow covering design, prototyping, and evaluation. This talk will conceptually explain AIDC’s overall vision, its approach to developing the design infrastructure, and the general direction of its research and development activities.
 Based on recent progress, including wafer evaluation results, the presentation will also discuss the significance of Japan’s advanced semiconductor R&D infrastructure and its future outlook. In addition, it will explore the potential role that open architectures—such as RISC-V—may play in future semiconductor design and research environments.

Kunio Uchiyama | Executive Director, AI Chip Design Laboratory (Invited Senior Researcher), National Institute of Advanced Industrial Science and Technology (AIST)
 The AI Chip Design Center (AIDC) is a NEDO-funded project jointly conducted by AIST and the University of Tokyo. Its objective is to accelerate AI chip development in Japan by providing small and medium-sized enterprises and startups with LSI design environments—such as EDA tools and logic emulators—as well as shared foundational technologies including AI chip design flows and SoC platforms. The center is located on the University of Tokyo’s Asano Campus, where facility development has been underway, and trial operations began in October 2019.
 Mr. Kunio Uchiyama received his master’s degree in Information Science from Tokyo Institute of Technology and holds a Ph.D. in Engineering. He joined Hitachi, Ltd. Central Research Laboratory in 1978, where he engaged in research on CAD, mainframes, microprocessors, and computer systems. After serving as Chief Engineer, Executive Officer, and Technical Advisor at Hitachi, he currently serves as an Invited Researcher at AIST and leads the NEDO-funded AI Chip Design Center. Kunio is a Fellow of the IEEE and the Institute of Electronics, Information and Communication Engineers (IEICE), and has also served as a member of the IEEE Computer Society Board of Governors.

The Future of AI Enabled by Open Compute: Chiplets, Scalable AI, and AI Development Platforms
The rapid adoption of generative AI and large-scale AI models is driving demand for computing platforms that go beyond traditional GPU-centric architectures, requiring greater flexibility, scalability, and power efficiency. In this talk, from the perspective of an AI accelerator designer, we introduce Tenstorrent’s approach to building an open AI computing platform, and discuss the role that RISC-V plays within this architecture. At Tenstorrent, a dataflow-oriented architecture optimized for AI computation is combined with RISC-V as the control and management plane, with the goal of enabling scalable and highly customizable AI systems. This presentation explains the design rationale behind choosing RISC-V over x86 or ARM, examining factors such as chiplet-based architectures, long-term extensibility, and support for security and confidential computing. The talk also addresses the importance of designing with the entire ecosystem in mind—including software stacks, compilers, and runtimes—and discusses how open standards influence the evolution of AI hardware. Finally, it offers a forward-looking perspective on how open hardware–software co-design centered on RISC-V may shape the future of AI, HPC, and data center computing. (Proposed title and abstract by the organizer)

Speaker: To be announced | Tenstorrent