発表題目
発表概要

発表者
経歴

Current Status and Future Policy Directions of Japan’s Semiconductor and Digital Industry Strategy
In 2025, Japan’s advanced semiconductor project Rapidus reached the stage of technical demonstration for advanced semiconductor manufacturing technologies at the 2-nanometer (2nm) node. This milestone is positioned as evidence that Japan’s semiconductor industry has made tangible progress in research and development, as well as in building manufacturing foundations for leading-edge process technologies. (Rapidus is a part of national project established to re-establish Japan’s capability in cutting-edge logic semiconductor manufacturing.)
 At the same time, a review of Japan’s semiconductor industry history shows that there have been numerous cases in which technological innovation was achieved, yet long-term business sustainability and international competitiveness were not fully secured. The gap between “being able to manufacture” and “being able to sustain a viable business” has been repeatedly identified as a structural challenge, and it remains a key issue in current industrial policy discussions.
 This lecture provides an organized overview and explanation of the current policy perspective and future direction for the advanced semiconductor sector, based on the Ministry of Economy, Trade and Industry (METI) document “Current Status and Future Outlook of the Semiconductor and Digital Industry Strategy.”
 The policy materials emphasize the need to progress in stages, covering advanced technology R&D, manufacturing infrastructure development, and commercialization. Within this framework, the technical validation of advanced manufacturing processes, including leading-edge nodes, is positioned as one of the critical milestones.
 The materials also repeatedly highlight that technical achievement alone is not the final objective. Rather, ensuring business autonomy and long-term sustainability is identified as an essential challenge that must be addressed alongside technological progress.
 Furthermore, the government places importance on building a semiconductor supply chain premised on international cooperation with allied and like-minded countries, rather than relying on a purely domestic, self-contained industrial structure. The documents indicate a shared recognition that strengthening competitiveness requires a holistic industry ecosystem approach, encompassing design, manufacturing, equipment, materials, and human capital.
 Based on these policy documents, this presentation examines how the two key axes—“establishing advanced technologies” and “securing business sustainability”—are structured and discussed.
This presentation does not propose new policy measures or future strategies, but aims to organize and explain the contents of publicly available policy materials. (Provisional title and abstract prepared by the conference organizer)

Speaker: To be announced

Development of Advanced Semiconductor Design Infrastructure and Ongoing Project Plans at AIDC
This presentation introduces the current status of semiconductor design environment development at the Advanced Integrated Device Consortium (AIDC), promoted by the National Institute of Advanced Industrial Science and Technology (AIST), as well as an overview of major projects currently underway.
 At AIDC, efforts are progressing to establish a digital design environment aligned with advanced semiconductor processes, and to build an end-to-end workflow covering design, prototyping, and evaluation. This talk will conceptually explain AIDC’s overall vision, its approach to developing the design infrastructure, and the general direction of its research and development activities.
 Based on recent progress, including wafer evaluation results, the presentation will also discuss the significance of Japan’s advanced semiconductor R&D infrastructure and its future outlook. In addition, it will explore the potential role that open architectures—such as RISC-V—may play in future semiconductor design and research environments.

Kunio Uchiyama | Executive Director, AI Chip Design Laboratory (Invited Senior Researcher), National Institute of Advanced Industrial Science and Technology (AIST)
 The AI Chip Design Center (AIDC) is a NEDO-funded project jointly conducted by AIST and the University of Tokyo. Its objective is to accelerate AI chip development in Japan by providing small and medium-sized enterprises and startups with LSI design environments—such as EDA tools and logic emulators—as well as shared foundational technologies including AI chip design flows and SoC platforms. The center is located on the University of Tokyo’s Asano Campus, where facility development has been underway, and trial operations began in October 2019.
 Mr. Kunio Uchiyama received his master’s degree in Information Science from Tokyo Institute of Technology and holds a Ph.D. in Engineering. He joined Hitachi, Ltd. Central Research Laboratory in 1978, where he engaged in research on CAD, mainframes, microprocessors, and computer systems. After serving as Chief Engineer, Executive Officer, and Technical Advisor at Hitachi, he currently serves as an Invited Researcher at AIST and leads the NEDO-funded AI Chip Design Center. Kunio is a Fellow of the IEEE and the Institute of Electronics, Information and Communication Engineers (IEICE), and has also served as a member of the IEEE Computer Society Board of Governors.

The Future of AI Enabled by Open Compute: Chiplets, Scalable AI, and AI Development Platforms
The rapid adoption of generative AI and large-scale AI models is driving demand for computing platforms that go beyond traditional GPU-centric architectures, requiring greater flexibility, scalability, and power efficiency. In this talk, from the perspective of an AI accelerator designer, we introduce Tenstorrent’s approach to building an open AI computing platform, and discuss the role that RISC-V plays within this architecture.
 At Tenstorrent, a dataflow-oriented architecture optimized for AI computation is combined with RISC-V as the control and management plane, with the goal of enabling scalable and highly customizable AI systems. This presentation explains the design rationale behind choosing RISC-V over x86 or ARM, examining factors such as chiplet-based architectures, long-term extensibility, and support for security and confidential computing.
 The talk also addresses the importance of designing with the entire ecosystem in mind—including software stacks, compilers, and runtimes—and discusses how open standards influence the evolution of AI hardware. Finally, it offers a forward-looking perspective on how open hardware–software co-design centered on RISC-V may shape the future of AI, HPC, and data center computing. (Proposed title and abstract by the organizer)

Speaker: To be announced | Tenstorrent

MIPS in the AI Era: Scalable Compute IP for AI, Robotics, and Edge Systems
 MIPS has a long history as an early RISC processor architecture and has recently been redefined as a RISC-V–based compute IP provider. Through its acquisition by GlobalFoundries and a range of strategic partnerships, MIPS now delivers multicore and data-movement subsystems designed to meet the demands of real-time, low-latency, and power-efficient computing in domains such as AI power delivery, industrial robotics, and automotive systems.
 This presentation explains how MIPS’s RISC-V IP portfolio is being used as scalable CPU and AI inference engines, particularly to enable highly efficient computing for autonomous systems and edge devices. It also discusses key design strategies—including multithreaded, coherent processing elements and accelerator integration—as well as ecosystem-building efforts across industry. Finally, the talk outlines future directions for AI, robotics, and edge computing enabled by MIPS technology. (Proposed title and abstract by the organizer)

Speaker: To be announced | MIPS Technology

Debugging in the Era of Open ISAs: RISC-V Software and System Bring-Up with TRACE32
 In mission-critical embedded systems such as automotive safety control, industrial automation, and medical devices, design reliability and correctness are of paramount importance. This presentation introduces methods for supporting the entire lifecycle of complex SoC and embedded software development using Lauterbach’s industry-standard debug and trace platform, TRACE32®.
 From early-stage RTL verification through final product safety certification, the session explains advanced solutions that visualize fine-grained hardware–software interactions, enabling real-time behavior analysis, verification, and debugging. TRACE32 supports a wide range of architectures—including RISC-V, ARM, and multicore/heterogeneous systems—and provides deep insight into system behavior through non-intrusive tracing of running systems.
 The presentation also covers trace analysis techniques and certified support packages that facilitate functional safety certification, demonstrating how TRACE32 helps ensure successful embedded system development in environments where reliability is critical.

Speaker: To be announced | Lauterbach Japan

Introduction to High-Performance Connectivity IP Enabling Chiplet Integration
 Chiplet technology is transforming semiconductor design by enabling modular, scalable architectures that can be deployed across a wide range of applications. This session introduces a reference architecture that integrates Alphawave’s chiplet IP across multiple foundries, and explains how it supports rapid development and first-silicon success.
The presentation focuses on advanced die-to-die (D2D) interconnect technologies that enable multi-die integration, as well as next-generation 224G high-speed connectivity technologies that support both scale-up and scale-out strategies. By leveraging silicon-proven IP and robust interconnect methodologies, this approach reduces design risk and accelerates innovation in next-generation semiconductor systems.

Jennifer Lee | VP of Sales and Korea/Japan Country Manager, Alphawave Semi
 Jennifer Lee is Vice President of Sales and Korea/Japan Country Manager at Alphawave Semi. She leads strategic customer engagement and drives business growth across key markets, with a particular focus on Korea.
 Ms. Lee brings more than 20 years of experience in the semiconductor IP industry, spanning design, field application engineering, and global sales. She began her career as an engineer and distinguished herself at Lucent Technologies and its spin-off, Agere Systems, where she was promoted to Distinguished Member of Technical Staff, a title awarded to exceptional technical contributors.
 Ms. Lee later held senior technical sales and leadership roles at Virage Logic (acquired by Synopsys), Cadence, Arm, and now Alphawave Semi. Ms. Lee holds a Master’s degree in Computer Engineering from the University of South Carolina. By combining a design-oriented mindset with a strong customer-centric approach, she has built long-term, value-driven partnerships across the semiconductor ecosystem.