Rapidus transistor manufacturing technology (1): Planar type, FinFET type and gate all-around type

Rapidus transistor manufacturing technology (1): About Planar type, FinFET type and Gate-All-Around type

IBM announced on May 6, 2021, the world’s first his 2-nanometer (nm) chip technology, a major advance in semiconductor design and processing. The technology is based on IBM’s second-generation nanosheet technology and incorporates a Gate-All-Around (GAA) nanosheet device architecture. This development would allow him to place his 50 billion transistors in an area the size of a fingernail, potentially significantly increasing performance and energy efficiency compared to existing semiconductor technologies. A “nanosheet” in the context of semiconductor technology refers to a very thin layer of semiconductor material. It is typically only a few nanometers thick. This term is often used, especially in advanced transistor design.

In conventional FETs (field effect transistors), the current flowing through the transistor is controlled by a component called the “gate.” This gate can turn the current on or off. Controlling this current becomes increasingly difficult as transistors are made smaller and more transistors are placed on a single chip (for faster, more efficient performance).

The nanosheet structure is an evolution of an earlier transistor architecture, FinFET (Fin Field Effect Transistor). In a FinFET, the gate surrounds three sides of a protrusion called a “fin.” Nanosheet designs take this a step further, with the gate material completely surrounding the flat, sheet-like channels. This “gate-all-around” (GAA) approach provides better control of current, improving performance and energy efficiency, especially for transistors with very small dimensions.

The development of nanosheet transistors is part of a continuing goal in semiconductor manufacturing to reduce transistor size while maintaining or increasing performance. Nanosheet transistors, used in cutting-edge technologies like IBM’s 2nm node chips, represent a significant advance in the ability to pack more power into smaller, more efficient devices.

To compare integrated circuits (ICs) using planar semiconductor technology to integrated circuits (ICs) using FinFET technology and nanosheet structures, several important aspects of semiconductor design and performance must be considered. Here’s a detailed comparison:

planar type

1. Structure: In planar transistor technology, the transistors are laid out in a flat two-dimensional plane. The gate of a transistor is directly above the semiconductor surface.

2. Performance and Scaling: Planar transistors have been the backbone of ICs for decades, but their performance begins to decline as they are scaled to smaller sizes. This is due to issues such as increased leakage current and difficulty controlling the flow of electrons in very small transistors.

3. Power Consumption: Planar transistors tend to have higher leakage currents, especially as they get smaller. This leads to increased power consumption, which can be disadvantageous for battery-powered devices.

4. Manufacturing Complexity: Manufacturing planar transistors is relatively simple and well understood given the maturity of the technology.

5. Cost: Planar technology is more cost-effective due to its simpler manufacturing process and established technology, especially for smaller transistor sizes.

FinFET type

In a FinFET, the gate surrounds three sides of a protrusion called a “fin.”

1. Structure: FinFET stands for “Fin Field-Effect Transistor”. In this design, conductive channels rise above the substrate to form thin “fins.” Gates wrap around his three sides of this fin, improving control of the channel.

2. Performance and Scaling: FinFETs allow further reduction in transistor size while maintaining performance. These provide better control of the current in the channel, reducing leakage and increasing switching speeds, which are important for modern high-performance ICs.

3. Power consumption: FinFETs typically have lower leakage currents compared to planar transistors, resulting in lower power consumption. This is especially beneficial for high-performance computing and mobile devices.

4. Manufacturing complexity: Manufacturing FinFETs is more complex and requires more advanced technology than planar transistors. This complexity increases as the node size decreases (7nm, 5nm, etc.).

5. Cost: The advanced manufacturing processes and equipment required for FinFETs result in high manufacturing costs, especially for small node sizes.

Gate all around type

IBM’s development of the world’s first 2 nanometer (nm) chip technology represents a major advance in semiconductor design and processing. This advancement was achieved using IBM’s second-generation nanosheet technology. The gate-all-around (GAA) nanosheet device architecture at the heart of this technology allows 50 billion transistors to be placed in an area the size of a fingernail. Key aspects of IBM’s GAA technology include:

1. Nanosheet architecture: The transition from traditional nanowire structures to nanosheet structures was a pivotal development. This architecture provides the electrostatic benefits of nanowires while also providing the density needed for improved performance.

2. Horizontal Stacked Gate-All-Around Design: The transistor architecture of this technology includes a new type of horizontally stacked GAA chip design. This design includes four gates on the transistor, allowing superior electrical signals to pass through and between other transistors on the chip.

3. Advances in transistor structure: IBM’s approach included the introduction of internal spacer modules into the transistor architecture. This is important to reduce the capacitance between the gate and source/drain and define the effective gate length of the GAA device. Additionally, a new dry internal spacer process was developed to provide sub-1 nm process control and an improved internal spacer profile.

4. Bottom dielectric isolation: This industry-first feature helped enable a gate length of 12 nm, equivalent to just 20 atoms. Full bottom dielectric isolation has a number of benefits, including reducing subchannel leakage and providing immunity to process variations.

5. Use of extreme ultraviolet (EUV) lithography: IBM implemented his EUV lithography in a front-end-of-line (FEOL) process, allowing precise control of nanosheet width. This advancement makes it easier to integrate low-power and high-performance designs on the same chip.

6. Delivering multi-threshold voltage (Multi-Vt) devices: This innovation in 2 nm transistors allows for different leakage levels, allowing device manufacturers to choose the appropriate performance level for their chip architecture.

2 nm chip technology offers significant improvements over existing semiconductor technologies. It is predicted to achieve 45% higher performance or 75% lower energy usage compared to state-of-the-art 7 nm node chips. The benefits of these advanced 2 nm chips range from improving battery life in mobile phones, reducing carbon emissions in data centers, and contributing to faster and more efficient computing in laptops and self-driving cars. may have a significant impact on the field.

This achievement is part of IBM’s long legacy in semiconductor innovation, marked by continued progress and collaboration in the field.


Planar, FinFET, and gate-all-around (GAA) transistors each have different structures and performance characteristics. A comparison of these techniques is shown below:

planar transistor

  • Structure: Traditional planar structure, with the transistor gate placed directly above the semiconductor surface.
  • Performance and Scaling: Miniaturization brings with it challenges such as increased leakage current and difficulty controlling electron flow.
  • Power Consumption: Miniaturized planar transistors tend to have increased leakage current, which can increase power consumption.
  • Manufacturing complexity: The manufacturing process is relatively simple and based on established technology.

FinFET type transistor

  • Structure: A 3D transistor called a fin, with the gate surrounding the fin.
  • Performance and Scaling: Fin construction allows for smaller size than planar designs, reduces leakage current and increases switching speed.
  • Power consumption: FinFETs have lower leakage current than planar types and are more power efficient overall.
  • Manufacturing Complexity: Compared to planar molds, they are more complex to manufacture and require more advanced technology.

Gate-all-around (GAA) transistor

  • Structure: In the GAA type, the gate completely surrounds the channel. This provides even better control of the current.
  • Performance and Scaling: The GAA type is a further evolution of the FinFET type, allowing for further miniaturization and improved performance.
  • Power Consumption: GAA types have very efficient power consumption, which is even better than FinFET types.
  • Manufacturing Complexity: Type GAA currently requires the most advanced and complex manufacturing process.

Each of these transistor technologies is selected depending on the specific application and performance requirements. Planar types are suitable for basic, cost-effective applications, while FinFET and GAA types are suitable for advanced applications requiring high performance and low power consumption.