RISC-V Days Vietnam Online 2020 Presenter / Contributor BIOs | RISC-V 協会

　
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KAMAKE no SUSUME Corp. offers event programming service including computer programming and gizmo-building classes for children and working adults, human resource activation events and training for local communities and companies, promotion of STEM education in collaboration with educational institutions and companies, and enriches people’s lives.

Takahiro Kitayama was born in Osaka, and completed the Department of Electrical and Electronic Engineering, Graduate School of Engineering, Kobe University, and joined Renesas Electronics Corporation in 2013. In 2014, he started with volunteer engineers on holidays. He founded “KAMAKE no SUSUME Corp.” in December 2017.

Keio University Faculty of Science and Technology Department of Information Engineering: Keio University Amano Lab researches new computer architecture in Post-Moore Age. As semiconductor scalings are stopping, it’s time to create new computers with special purpose, reduced power, and dynamic structure. His team is not only conducting simulation but also creating actual LSI chip and board, system construction and verification.

Prof. Hideharu Amano received his Ph.D. in 1986 from Keio University. He was a visiting assistant professor at Stanford University from 1989-1990. Now, he is a professor at the Department of Information and Computer Science, Keio University. Hideharu Amano started research on computer architecture under the professor Hideo Aiso, Department of Electrical Engineering, and shared memory, cache, switch chip, multiprocessor, reconfigurable system, massively parallel system, router chip, multi-context device, power saving Reconfigurable accelerator, ultra-low power processor, consistent architecture research. It is known for its approach to developing and evaluating real systems to demonstrate ideas. In addition to translating Hennessy Patterson’s “quantitative approach”, he has held numerous academic committee positions and positions.

In March 2020, the RISC-V International Association was incorporated in Switzerland. This move is reflective of community concern and managing strategic risk for our community investing in RISC-V for the next 50+ years. Origin of RISC-V goes back to May 2010, when Prof. Krste Asanović and graduate students Yunsup Lee and Andrew Waterman started the RISC-V instruction set at UC Berkeley, of which Prof. David Patterson was Director. The RISC-V Foundation (www.riscv.org) was founded in 2015 to build an open, collaborative community of software and hardware innovators based on the RISC-V ISA. The Foundation, a non-profit corporation controlled by its members, directed the development to drive the initial adoption of the RISC-V ISA.

RISC-V International Chairman of the Board Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a Ph.D. in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007, where he co-founded the Berkeley Par Lab and then led the ASPIRE lab. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently Co-Director of the Berkeley ADEPT lab, tackling the challenge of creating and deploying specialized processors, and is also an Associate Director at the Berkeley Wireless Research Center. He leads the free RISC-V ISA project at Berkeley, is Chairman of the RISC-V Foundation, and is Chief Architect and a co-founder at SiFive Inc. He is an ACM Fellow and an IEEE Fellow.

Key Laboratory for Smart Integrated Systems (SISLAB) is one of the 7 key laboratories of Vietnam National University, Hanoi. The SIS laboratory offers programs in VLSI/ASIC systems design, Signal & image processing, Intelligent transmitting networks and systems, Knowledge Technology, and Embedded systems.

Duy-Hieu Bui received a Ph.D. degree in Nanotechnology and Nanoelectronics from University Grenoble Alpes, France (in collaboration with CEA-Leti and VNU-UET) in 2019. He is working as a research engineer at the VNU-key Laboratory for Smart Integrated Systems (SISLAB), VNU-UET. He previously worked at SISLAB, VNU-UET (2010-2015) on VLSI design for multimedia applications, and at CEA-Leti, MINATEC, France (2015-2017) on low-power security hardware and hardware security. He has been a principal engineer in various projects on low-power hardware design for multimedia, security and artificial intelligence at SISLAB including VENGME, ADEN4IOT, and SCAI. His research interests include hardware/software co-design and verification, embedded systems, low-power solutions for artificial intelligence, VLSI system/circuit designs for information security and hardware security.

In the new World University Research Rankings 2020, Technical University of Denmark (DTU) ranks second in the world after Massachusetts Institute of Technology (MIT) and number one in Europe. DTU scores high in multidisciplinary and collaborativeness. DTU Compute is an academic environment spanning mathematics, statistics, computer science, and engineering. Interdisciplinary research areas are big data and data science, artificial intelligence (AI), internet of things (IoT), smart and secure societies, smart manufacturing and life sciences.

Martin Schoeberl is an associate professor with the Department of Applied Mathematics and Computer Science, Technical University of Denmark, Lyngby, Denmark. His research interests include hard real-time systems, time-predictable computer architecture, and real-time Java. He received a PhD and a Habilitation degree in computer engineering from the Vienna University of Technology, Vienna, Austria. He is a member of the IEEE and the ACM. (Based on document published on 10 January 2018).

VLSI Technology Page is established to share the knowledge and experience of the digital integrated circuit design. We create the small projects to investigate and study before publishing them as the open-source. We are focusing on the design and verification by using flexible language such as Verilog, SystemVerilog, SystemC and script languages. “Share to develop together” is our slogan. Now, VLSI Technology page is developing the open-source SoC based on the RISC-V cores. Vanguard (VG) SoC is the first project in our long-term plan.

Quynh Do-ngoc is an RTL design and verification engineer. He is currently evaluating a 32/64-bit RISC-V SoC using an open source CPU core. Quynh has previously worked on 32-bit high-speed and low-power super-scalar micro-processor with L1 and L2 cache memories, BitCoin miner chip with multi-core of SHA256 on FPGA board and numerous project. He has submitted academic papers.

Fifteen years in business and a founding Premier member of RISC-V International, Andes Technology is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, dual-issue and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 1 billion since 2018. For more information, please visit https://www.andestech.com

Florian Wohlrab is one of the first RISC-V Ambassadors and Head of Sales for EMEA and Japan at Andes Technology. His mission is to help bring RISC-V towards mainstream and enable others to easily get started within the RISC-V ecosystem. He is fascinated by the open, modular, compact and innovative RISC-V CPU designs. Before joining Andes Technology he worked in industrial PC and IoT fields, holding various technical and business roles within Europe and Asia.

Riken Computational Molecular Design Group aims to simulate biomolecular interactions and to design effective molecular regulators using large-scale computer simulations. The team is designing novel compounds for various target biomolecules by utilizing our computational techniques. By developing exclusive high-performance computers, the team aims to achieve unprecedented long-term MD simulations.

Since 2013, Makoto Tajii has been in his current position of Group Director, System Computational Biology Research Group, RIKEN and Life Modeling Core, Life Systems Research Center . Makoto’s field of study are Computational biology, and Computer architecture. Makoto is a recipient of Gordon Bell Awards: 1995 (Special-Purpose Machine) / 2006 (Peak Performance Honorable Mention) / 2009 (Price Performance).

University of Electro-Communication (UEC) has its previous roots in the Technical Institute for Wireless-Communications, founded to train wireless communication engineers in 1918. Today the university focuses on “Diversity Communication, and Innovations” to nurture innovative social leaders. UEC offers fundamental science, applied engineering, physics, material science, life science, optical science, electronics, robotics, mechanical engineering, and media science.

CKRISTIAN DURAN (Student Member, IEEE) received the B.Sc. degree in electronics and the M.S degree in telecommunications from the Universidad Industrial de Santander (UIS), Bucaramanga, Colombia, in 2014 and 2017, respectively. He is currently pursuing the Ph.D. degree in electronics engineering with the Universidad Industrial de Santander (UIS), Bucaramanga, and also a Research Assistant with the University of Electro-Comunications (UEC), Tokyo, Japan.

Quan Nguyen-hung is specialized in Logic and RTL design. He writes in Verilog HDL, SystemVerilog, SystemC, Perl, C-shell, Tcl. He designed silicon proven UART, CAN, SRAM/Flash controller, SDRAM controller, SSPI, privite data encryption of HF RFID Tag chip, the authentication algorithm and memory management of UHF RFID Tag chip, digital interface of ROM chip, digital interface of ADC chip, Error/ECC controller. He also has FPGA implementation designs: DES, AES encryption, JTAG/debugger of 8-bit MCU.

The University of Tsukuba was established in October 1973, due to the relocation of its antecedent to the Tsukuba area. The university’s history dates back to its founding as a Normal School in 1872. As the new concept comprehensive university in Japan to be established under a country-wide university reform plan, the University has featured “Openness” with “New Systems for Education and Research.” The university reform plays a major role in our continuing effort for improvement. We are striving to achieve a unique, active, and internationally competitive university with superlative education and research facilities.

Riadh Ben Abdelhamid received his Bachelor of Electrical Engineering degree from the National Engineering School of Tunis (ENIT) in 2010. Until 2015, he was an FPGA design and verification engineer in a large Europe-based avionics company contributing to the design of safety critical systems including a flight control system. Since 2015, he joined a synopsys validation team on their flagship FPGA emulation system ZEBU. In 2017, he was selected as a Japanese Government Scholarship (MEXT) recipient to study in Japan. As a result, he obtained his Master of Engineering degree in Computer Science from the University of Tsukuba in March 2020. He is currently enrolled as a Ph.D candidate at the same university. His research interest includes many-core processor architectures and overlays, High-Performance Computing, reconfigurable accelerators as well as AI applications in VLSI design. He is also enthusiast about making his own many-core processor chip start-up.

The VNU University of Engineering and Technology is a member of Vietnam National University of Hanoi (VNU). The Faculty of Information Technology was established on February 11, 1995 at VNU University of Science and was re-established on September 9, 2004. Inheriting Faculty of earlier “Mathematics – Mechanics” (1960-1980) and later “Mathematics – Mechanics – Informatics” (1980-1995) and of the Institute of Informatics and Electronics (1990-1995) at the former University of Hanoi (from 1956). Every year, about 350 undergraduate students, 150 master students and 10 Ph.D. students are admitted to the faculty with the broad range of teaching programs. Faculty of Information Technology has collaborations in teaching and research with JAIST, Tohoku University (Japan), UNU-IIST, University of New South Wales, National University of Singapore, University of Twente, etc. The faculty carries out joint research projects with IBM, Mitani-Sangyo, NEC, Panasonic and Toshiba, Tinh Van Group, HiPT Group, FSoft and others.

Xuan-Tu Tran received a Ph.D. degree in 2008 from Grenoble INP (in collaboration with the CEA-LETI), France, in Micro Nano Electronics. Xuan-Tu Tran is currently an associate professor at the Faculty of Electronics and Telecommunications, VNU University of Engineering and Technology (VNU-UET), a member university of Vietnam National University, Hanoi (VNU). More information: http://www.uet.vnu.edu.vn/~tutx

AIST Research Institute for Secure Systems (RISEC) was founded in 2012 inheriting former three research center to focus on protecting IT information assets in uses of cryptography in internet and cloud service, control system security to protect social infrastructures such as electricity, railways, water district from cyber attacks, countermeasures for IC cards, system design methodology to prevent errors injected at design stages and operational stages, and countermeasures to threats from future quantum computing technologies. Focus is on the technologies used in the real industries and society.

Akira Tsukamoto received the M.S. degree in computer science from Columbia University in the City of New York. He works at the National Institute of Advanced Industrial Science and Technology (AIST). His main focusing area is software engineering on networks, operating systems, and system security, who enthusiastic on any kind of technical development and have worked on products based on Cell/B.E. and ARM.

The University of Electro-Communications holds a mission to aim for the creation and achievement of knowledge and skill to contribute to the sustainable development of humankind.

Trong-Thuc Hoang received the B.Sc. degree in electronics and telecommunications and the M.S. degree in microelectronics from the University of Science – Vietnam National University of Ho Chi Minh City, Vietnam, in 2012 and 2017, respectively. He is currently pursuing the Ph.D. degree in information and network engineering with The University of Electro-Communications (UEC), Tokyo, Japan, and also a Research Assistant with the National Institute of Advanced Industrial Science and Technology (AIST), Tokyo, Japan.

Advanced SIMD architecture derived by applying RISC-V architecture

This presentation introduces an advanced Single-Instruction Multiple Data (SIMD) -based RISC-V design in conjunction with tightly-connected many-core interconnect. The proposed concept, Dual-Instruction Multiple Data (DIMD), increases the efficiency of parallel computation, which can reduce calculation time dramatically compared to traditional SIMD. Compared to other ISAs, RISC-V ISA relieves the bottleneck of our parallel program implementation. The design concept, performance will be shown for FFT computation on the proposed DIMD architecture running on FPGA.

Yoshiki Yamaguchi is an associate professor at the University of Tsukuba. He received a Ph.D. in engineering from the University of Tsukuba in 2003. Then, he was a Research Scientist with the Yokohama Institute, RIKEN. Since 2005, he returned to join the faculty at the Graduate School of System and Information Engineering, University of Tsukuba. Since 2011, he has been a Collaborative Fellow at the Center for Computational Science, University of Tsukuba. His research interests include reconfigurable architecture and systems for real-time applications and highly power-efficient computing. He is also interested in heterogeneous high-performance computing, including the fusion of FPGA, GPU, and CPUs.

ASA Microsystems, Inc. is headquartered in Silicon Valley, California with R&D center in Yokohama, Japan. ASA’s patent-pending proprietary microarchitecture provides the highest performance RISC V processor with the lowest power and smallest size. ASA offers configurable low power RISC-V processors with custom accelerator engines and SoC for IoT and edge AI. All the cores and IPs are seamlessly migratable from FPGA to ASIC/SoC. We also offer custom emulation software for RTL verification and application software development at the same time.

Ashraful Islam is Co-Founder and CTO of ASA Microsystems Inc. Ashraful has 10+ years of experience in the processor, ASIC & SoC design, and Verification. He has graduated from the University of Rajshahi, Bangladesh. He is currently enrolled in the Ph.D. program at the Tokyo Institute of Technology, Japan. His research interests include microprocessors, Computer Architecture, low power multi-processing systems in the area of high computing applications.

In November 2019, Technology Research Association of Secure IoT Edge application based on RISC-V Open architecture (TRASIO) was incorporated to build an open security infrastructure. TRASIO’s members are Denso’s semiconductor design subsidiaries NSITEXE, Keio University, National Institute of Advanced Industrial Science and Technology (AIST), SECOM, and Hitachi. TRASIO aims to implement test research to white-box security hardware and software infrastructure technology by utilizing RISC-V open architecture.

Kuniyasu Suzaki received the B.E. and M.E. degrees in computer science from Tokyo University of Agriculture and Technology, and the Ph.D. degree in computer science from The University of Tokyo, Tokyo, Japan. He is currently a Senior Researcher at the National Institute of Advanced Industrial Science and Technology (AIST) and a Researcher of the Technology Research Association of Secure IoT Edge Application based on RISC-V Open Architecture (TRASIO). His research interests include security on CPU, operating systems, and hypervisor.

SH Consulting Vietnam Company Limited(SHC) is a company that supports RISC-V embedded software development from Vietnam. Its development center is located in QTSC. Their recent development includes AWS FreeRTOS IoT for RISC-V, Xtensa and ARM. Previously the team developed QNX, .NETMF, UEFI, uiTRON, and Linux.

Shumpei Kawasaki co-founded SH Consulting in 2013. He specialized in the field of security for RISC-V FPGAs / SoCs. In 1990s, he co-developed CPUs and chipsets for Sega Saturn and Dreamcast video games. ARM adopted his “16-bit fixed-length instruction” invention for their monumentally successful “ARM7TDMI” and “ARM9TDMI.” In 2000s Shumpei led a development of a minimal operating system for Root of Trust chips used in network routers, 2-5G mobile handsets, and secure tokens in US.

Thang Tran is a principal engineer at Andes Technology Corp. He received his MBA from St. Edwards University in 1985 and Ph.D. in Computer and Electrical Engineering from University of Texas at Austin in 1992. He is specialized in microprocessor architecture and design and has over 35 years of experiences at Motorola, AMD, Intel, ADI, Centaur Technologies, TI, MediaTek, Freescale Semiconductor, and Synopsys. His notable microprocessors are AMD Athlon, ARM Cortex-A8, and ARC HS. He has designed microprocessors with different types of instruction sets: ARC, ARM, PowerPC, x86, MIPS, ADI-DSP, and RISC-V vector extension. He also has taught MIPS microprocessor design at Viet Nam National University in Ho Chi Minh City and Computer Architecture at Santa Clara University in California (adjunct professor). Thang has 160+ granted patents and many more pending patent applications.

YUXI TAN received the B.S. degree in the speciality of Electrical Engineering
and Automation from the Beihang University, Beijing, China, in 2017.
He is currently pursuing the M.S. degree in the Engineering of
Computer Science at the University of Tsukuba. His research is about
high performance many-core architecture on FPGA.

In March 2020, RISC-V International was incorporated in Switzerland based on no one country, company, government, or event. This move is reflective of community investing in RISC-V for the next 50+ years.

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement. across the industry.

The University of Electro-Communications Integrated Circuit Design Laboratory educates the design, implementation, and evaluation of hardware systems and VLSI, aims to design “system on chip” by integrating various information processing hardware, and develops a high-performance computational circuit realized with a small number of elements.

Cong-Kha Pham is a professor at the University of Electro-Communications is studying hardware system design implementation by FPGA and integrated circuits Recent projects include research on energy harvest power supply and low-power data-centric sensor network system utilizing it, development of long distance transmission / miniaturization equipment of sensor network by low power wireless, super low-voltage device project, research on memory-based information detection system, hardware implementation of hardware system by FPGA and integrated circuit, etc. Professor Pham is teaching many undergraduate and postgraduate students and has received numerous award for dissertation.