RISC-V Day Tokyo 2020 Virtual Booths Details | RISC-V 協会

Stay Ahead with the Latest Advances in RISC-V Development Tools

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Booth opening date and time:
11/5 (Wed) 10:00 – 16:00
11/6 (Fri) 10:00 – 16:00
Booth attendant:
IAR Systems Japan Office
Koichi Matsuo,
Engineering Department
Katsutoshi Furue,
Marketing Department

Every developer needs their application to be fast, compact, and energy-friendly. Using a highly optimized compiler and a comprehensive debugger along with fully-integrated analysis tools will help you ensure the quality and efficiency of the code you are developing. We give you access to the complete set of build tools, code analysis and debugging tools from one feature-rich IDE, enabling you to speed up time-to-market and therefore spend your time on the innovative parts that will differentiate your product.
All developers have a lot to gain by having access to professional development tools with professional technical support from a long-term vendor they can rely on. This session is for anyone interested in learning more about the possibilities offered when using professional development tools.

SiFive State-of-the-Art showcase

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Booth Open at:
11/5(Thur) : 17:30-18:30pm
11/6(Fri)：16:30-17:30pm

Booth Attendants:
Member of LSI Design Service Department

As a leading RISC-V company, SiFive ™ has announced the following cutting-edge technologies: “Core Designer 20G1 Release” and recent 7 series enhancements (20G1 6.0), “SiFive Intelligence VI Series Core” SiFiveShield ™ & quot; Comprehensive Security Solution for a wide range of applications from AI to HPC, “SiFive Shield ™” More and more “SiFiveAdvancedTrace and Debugsolution” … Here are the details of these technologies !!

AdaCore RISC-V Ada / C language software development tool introduction: Model base, formal verification, support for various safety standards

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Booth Opens:
November 5-6

10am-5pm

Booth Attendants
ITAccess

AdaCore’s initial product offerings include GNAT Pro Ada and GNAT Pro C targeted to bare metal RISC-V 32- and 64-bit architectures (for more information see https://www.adacore.com/gnatpro), as well as the GNAT Community edition for bare metal RISC-V 32-bit configurations. The latter is free of charge and can be downloaded from https://www.adacore.com/community. For GNAT Pro customers with software safety certification requirements, run-time library certification and tool qualification materials are available as an add-on for standards in industries such as avionics (DO-178C/ED-12C), railway (EN-50128) and automotive (ISO-26262).

SHC RISC-V Demo: Securely Connect Andes N22 RISC-V to Amazon AWS IoT Cloud with Root of Trust Chip

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Booth Opens:
November 5th-6th

2pm-4pm

Booth Attendant
Hoan Huynh
SH Consulting
Vietnam

This demo shows a Secure IoT solution using a Corvette-F1 board, evaluation kit with full support for the 32-bit AndesCore N25 and the AndeShape AE250 Platform, runs Amazon FreeRTOS, which is an open source operating system for microcontrollers from Amazon Web Services (AWS). It uses an ESP32-WROOM board as an external Wi-fi module. ATECC608A-MAHDA chip is integrated such as Trusted Platform Module (TPM) to provide hardware-based endpoint device security. This integration ensures the private key used to establish device identity can be securely stored in tamper-proof hardware devices to prevent it from being taken out of the devices for impersonation and other malicious activities.

In IoT solution deployments, it is important to check the identity of the device that is communicating with the messaging gateway. For the first time running demo, TPM will generate key pairs for the devices, which are then used to authenticate and encrypt the traffic. The keys are generated inside the TPM itself and are thereby protected from being retrieved by external programs. In fact, even without harnessing the capabilities of a hardware root of trust and secure boot, the TPM is also valuable just as a hardware key store. The private keys are protected by the hardware and offer far better protection than a software key. This integration uses the PKCS#11 protocol as the interface to the TPM.

After generating key pairs, this demo uses the FreeRTOS MQTT library to connect to the AWS Cloud and then periodically publish messages to an MQTT topic hosted by the AWS IoT MQTT broker. A specific Android application developed by SHC also uses this topic to communicate with Corvette-F1 board to control its on-board LEDs.

RISC-V based custom SoC development tool by Chipyard Development of learning accelerator for Bayesian neural network

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Booth Opens:
11/5-6 2pm-4pm

Booth Attendant:
Nishida Keigo
Research Associate
Laboratory for Computational Molecular Design
RIKEN Center for Biosystems Dynamics Research

Bayesian neural networks (Bayesian NN), which learn parameter uncertainties, are expected to be important in practical applications of deep learning, but they are very computationally expensive and unwieldy models. We are proceeding with a project to streamline Bayesian NN learning with dedicated hardware, and we will give a brief introduction. In addition, we use Chipyard, a RISC-V custom SoC development tool, to carry out the project, and we will briefly introduce how we are actually using the tool project.

Introduction of RISC-V version VxWorks 7 real-time OS and Workbench 4 development environment

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No Live Demo
Please contact to Wind River

VxWorks 7 is an embedded real-time operating system that features fast real-time scheduling and a rich runtime library. Select and build components from the GUI in the cross-development environment Workbench 4, and download the VxWorks image to SiFive’s HiFive target board via Ethernet. After booting the 64-bit SMP kernel, we will introduce the visualization of real-time processing by System Viewer and the remote debugging function of the application.

RISC-V development with ASIP Designer tools Q and A time

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Booth Open:
November 5th – 6th 3pm-5pmBooth Attendant:
Mitsuru Tomono
Senior Application Engineer, Solutions Group Processor Solutions, Nippon Synopsys

As a pre-sales application engineer for Synopsys processor solutions, we have over two years of experience in Synopsys ASIP Designer tools and the ARC processor family, especially embedded vision processors for AI applications, and many in-vehicle and image processing-focused embedded equipment customers. Worked with to achieve many design requirements.

Rapid prototyping and testing of the AR32Z with ARSIM

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Booth Opens:
TBD

Booth Attendants
TBD

ASA Microsystems, Inc. Is headquartered in Silicon Valley, California. There is an R & amp; D center in Yokohama, Japan. ASA’s unique patent-pending microarchitecture is the highest performing RISCV processor with minimal power and minimum size. The ASA provides what is configurable. A low power RISC-V processor with a custom accelerator engine and SoC for IoT and edge AI. All core IPs can be seamlessly migrated from FPGA to ASIC / SoC. We also offer custom emulation software. RTL verification and application software development can be performed at the same time.

Ariel IoT SoC Development Platform Featuring Andes N25F RISC-V Core

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Booth Opens:
6th 10:00-16:00

Booth Attendants
Florian Wohlrab
Head of Sales for EMEA and Japan at Andes Technology

Andes Technology Corporation is a world-class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve the rapidly growing global embedded system applications. The company delivers superior low power CPU cores, including the comprehensive RISC-V V5 family of processor IPs, with integrated development environment and associated software/hardware solutions for efficient SoC design. Up to the end of 2019, the cumulative volume of Andes-Embedded™ SoCs has surpassed the 5-billion mark. Andes Technology’s comprehensive CPU line includes extensible entry-level, mid-range and high-end families. For more information, please visit www.andestech.com