RISC-V Day Tokyo 2025 Autumn (Private) | RISC-V 協会

Tuesday, December 4, 2025 9:00-18:00
Japan Standard Time (UTC+9)
Bunkyo-ku, Tokyo University of Tokyo Ito HallCall for Poster | Proposals
Registration

Mission and Vision of the RISC-V Alliance Japan

① Promotion of technologies that enable RISC-V

② Promotion of technologies that RISC-V enables

③ Promotion of RISC-V technologies

④ Promotion of computer security

⑤ Promotion of social implementation through software and electronics

Venue Map

Presentation Titles, and Speakers (without honorifics)

Icon	Presentation Title	Speaker
	Japan’s Semiconductor Strategy 2025 — Building the Technologies, Policies, and Industrial Ecosystem to Support Next-Generation Semiconductor Manufacturing	Hisashi Saito \| Commerce and Information Policy Bureau, Minister of Economy, Trade and Industry (being arranaged)
	Caliptra and OpenTitan Tutorial — Architecture and Integration of the Open Root of Trust Firmware Led by Google and Microsoft.	Andrés Lagar-Cavilla \| Distinguished Engineer \| Google LLC Mountain View, California, USA
	Panel Discussion: Toward a Standard RISC-V Platform — Understanding and Implementing the RVA23 Linux-Class Profile	RISC-V Alliance Japan
	Activities of RISC-V Working Group of Japan Embedded Systems Technology Associations (JASA)	RISC-V Working Group: Japan Embedded Systems Technology Associations (JASA)
	Hands-on Tutorial and Demo: OpenROAD and Tiny Tapeout Workflow	Noritsuna Imamura, ISHI-Kai

Abstract of the Presentation

Icon	Presentation Title, Entity and Abstract
	Japan’s Semiconductor Strategy 2025 by METI Commerce and Information Policy Bureau, Minister of Economy, Trade and Industry This presentation reports on the key points of Japan’s “Semiconductor Strategy 2025,” promoted by METI. Against the backdrop of rapid digitalization and growing importance of economic security, the Japanese government positions semiconductors as “the rice of all industries” and aims to strengthen national competitiveness. Industry, academia, and government are working together under three main pillars: (1) enhancing semiconductor technology and manufacturing capabilities, (2) developing digital infrastructure, and (3) fostering the software and IT industries. The session will share the direction of ongoing policy discussions and future outlook.
	Caliptra and OpenTitan Tutorial \| Google LLC Mountain View, California, USA This tutorial will focus on Caliptra, an open Root of Trust (RoT) project under the Open Compute Project (OCP) led by Google and Microsoft, and supported by major semiconductor companies such as NVIDIA and AMD, as well as on OpenTitan, an independent RoT chip initiative led by Google and now being mass-produced by Nuvoton.Caliptra is designed as an SoC-embedded stack that includes firmware, provisioning, and Linux integration, whereas OpenTitan aims to provide a standalone security chip. While OpenTitan represents a transparent, discrete RoT implementation, Caliptra targets the standardization of integrated RoT solutions for cloud and datacenter systems. This session will explore both projects’ design philosophies, secure boot mechanisms, and approaches to improving trust through open-source development.
	Panel Discussion \| RISC-V Association Japan This panel will reexamine the significance of the Linux-class RISC-V platform defined by RVA23. While the standardization of ISA extensions continues to advance, it is the standardization of non-ISA domains—such as I/O, memory, networking, and coherence—that will ultimately determine implementation interoperability. The session will explore the current state and challenges of platform standardization within the RISC-V ecosystem from both hardware and software perspectives.
	Activities of RISC-V Working Group of JASA RISC-V Working Group \| Japan Embedded Systems Technology Associations (JASA) \| In recent years, the JASA RISC-V Working Group, efforts have focused on promoting understanding of RISC-V and validating implementation technologies. The group first implemented a RISC-V processor on FPGA, followed by a prototype chip fabricated through the Google Shuttle program, on which functional demonstrations and software evaluations were conducted. Currently, the group is developing an original in-house RISC-V chip design, achieving successful demonstrations at each stage. This presentation will highlight these achievements and discuss future development plans.
	Hands-on Tutorial and Demo: OpenROAD and Tiny Tapeout Workflow \| ISHI-Kai This hands-on tutorial uses the open-source EDA tool OpenROAD and the educational Tiny Tapeout platform to guide participants through the fundamental workflow from LSI design to chip fabrication. Participants will gain practical experience with design automation, physical implementation, and verification processes by performing each step interactively. The goal is to provide a hands-on understanding of open-source hardware design methodologies. (Advance registration is recommended.)

Icon	Speakers’ Profiles
	Japan’s Semiconductor Strategy 2025 by METI Commerce and Information Policy Bureau, Minister of Economy, Trade and Industry This presentation reports on the key points of Japan’s “Semiconductor Strategy 2025,” promoted by METI. Against the backdrop of rapid digitalization and growing importance of economic security, the Japanese government positions semiconductors as “the rice of all industries” and aims to strengthen national competitiveness. Industry, academia, and government are working together under three main pillars: (1) enhancing semiconductor technology and manufacturing capabilities, (2) developing digital infrastructure, and (3) fostering the software and IT industries. The session will share the direction of ongoing policy discussions and future outlook.
	Caliptra and OpenTitan Tutorial \| Google LLC Mountain View, California, USA This tutorial will focus on Caliptra, an open Root of Trust (RoT) project under the Open Compute Project (OCP) led by Google and Microsoft, and supported by major semiconductor companies such as NVIDIA and AMD, as well as on OpenTitan, an independent RoT chip initiative led by Google and now being mass-produced by Nuvoton.Caliptra is designed as an SoC-embedded stack that includes firmware, provisioning, and Linux integration, whereas OpenTitan aims to provide a standalone security chip. While OpenTitan represents a transparent, discrete RoT implementation, Caliptra targets the standardization of integrated RoT solutions for cloud and datacenter systems. This session will explore both projects’ design philosophies, secure boot mechanisms, and approaches to improving trust through open-source development.
	Panel Discussion \| RISC-V Association Japan This panel will reexamine the significance of the Linux-class RISC-V platform defined by RVA23. While the standardization of ISA extensions continues to advance, it is the standardization of non-ISA domains—such as I/O, memory, networking, and coherence—that will ultimately determine implementation interoperability. The session will explore the current state and challenges of platform standardization within the RISC-V ecosystem from both hardware and software perspectives.
	Activities of RISC-V Working Group of JASA RISC-V Working Group \| Japan Embedded Systems Technology Associations (JASA) \| In recent years, the JASA RISC-V Working Group, efforts have focused on promoting understanding of RISC-V and validating implementation technologies. The group first implemented a RISC-V processor on FPGA, followed by a prototype chip fabricated through the Google Shuttle program, on which functional demonstrations and software evaluations were conducted. Currently, the group is developing an original in-house RISC-V chip design, achieving successful demonstrations at each stage. This presentation will highlight these achievements and discuss future development plans.
	Hands-on Tutorial and Demo: OpenROAD and Tiny Tapeout Workflow \| ISHI-Kai This hands-on tutorial uses the open-source EDA tool OpenROAD and the educational Tiny Tapeout platform to guide participants through the fundamental workflow from LSI design to chip fabrication. Participants will gain practical experience with design automation, physical implementation, and verification processes by performing each step interactively. The goal is to provide a hands-on understanding of open-source hardware design methodologies. (Advance registration is recommended.)

Icon	Presentation Title, Entity and Abstract
	Japan’s Semiconductor Strategy 2025 by METI Commerce and Information Policy Bureau, Minister of Economy, Trade and Industry This presentation reports on the key points of Japan’s “Semiconductor Strategy 2025,” promoted by METI. Against the backdrop of rapid digitalization and growing importance of economic security, the Japanese government positions semiconductors as “the rice of all industries” and aims to strengthen national competitiveness. Industry, academia, and government are working together under three main pillars: (1) enhancing semiconductor technology and manufacturing capabilities, (2) developing digital infrastructure, and (3) fostering the software and IT industries. The session will share the direction of ongoing policy discussions and future outlook.
	Caliptra and OpenTitan Tutorial \| Google LLC Mountain View, California, USA This tutorial will focus on Caliptra, an open Root of Trust (RoT) project under the Open Compute Project (OCP) led by Google and Microsoft, and supported by major semiconductor companies such as NVIDIA and AMD, as well as on OpenTitan, an independent RoT chip initiative led by Google and now being mass-produced by Nuvoton.Caliptra is designed as an SoC-embedded stack that includes firmware, provisioning, and Linux integration, whereas OpenTitan aims to provide a standalone security chip. While OpenTitan represents a transparent, discrete RoT implementation, Caliptra targets the standardization of integrated RoT solutions for cloud and datacenter systems. This session will explore both projects’ design philosophies, secure boot mechanisms, and approaches to improving trust through open-source development.
	Panel Discussion \| RISC-V Association Japan This panel will reexamine the significance of the Linux-class RISC-V platform defined by RVA23. While the standardization of ISA extensions continues to advance, it is the standardization of non-ISA domains—such as I/O, memory, networking, and coherence—that will ultimately determine implementation interoperability. The session will explore the current state and challenges of platform standardization within the RISC-V ecosystem from both hardware and software perspectives.
	Activities of RISC-V Working Group of JASA RISC-V Working Group \| Japan Embedded Systems Technology Associations (JASA) \| In recent years, the JASA RISC-V Working Group, efforts have focused on promoting understanding of RISC-V and validating implementation technologies. The group first implemented a RISC-V processor on FPGA, followed by a prototype chip fabricated through the Google Shuttle program, on which functional demonstrations and software evaluations were conducted. Currently, the group is developing an original in-house RISC-V chip design, achieving successful demonstrations at each stage. This presentation will highlight these achievements and discuss future development plans.
	Hands-on Tutorial and Demo: OpenROAD and Tiny Tapeout Workflow \| ISHI-Kai This hands-on tutorial uses the open-source EDA tool OpenROAD and the educational Tiny Tapeout platform to guide participants through the fundamental workflow from LSI design to chip fabrication. Participants will gain practical experience with design automation, physical implementation, and verification processes by performing each step interactively. The goal is to provide a hands-on understanding of open-source hardware design methodologies. (Advance registration is recommended.)

Icon	Speakers’ Profiles
	Japan’s Semiconductor Strategy 2025 by METI Commerce and Information Policy Bureau, Minister of Economy, Trade and Industry This presentation reports on the key points of Japan’s “Semiconductor Strategy 2025,” promoted by METI. Against the backdrop of rapid digitalization and growing importance of economic security, the Japanese government positions semiconductors as “the rice of all industries” and aims to strengthen national competitiveness. Industry, academia, and government are working together under three main pillars: (1) enhancing semiconductor technology and manufacturing capabilities, (2) developing digital infrastructure, and (3) fostering the software and IT industries. The session will share the direction of ongoing policy discussions and future outlook.
	Caliptra and OpenTitan Tutorial \| Google LLC Mountain View, California, USA This tutorial will focus on Caliptra, an open Root of Trust (RoT) project under the Open Compute Project (OCP) led by Google and Microsoft, and supported by major semiconductor companies such as NVIDIA and AMD, as well as on OpenTitan, an independent RoT chip initiative led by Google and now being mass-produced by Nuvoton.Caliptra is designed as an SoC-embedded stack that includes firmware, provisioning, and Linux integration, whereas OpenTitan aims to provide a standalone security chip. While OpenTitan represents a transparent, discrete RoT implementation, Caliptra targets the standardization of integrated RoT solutions for cloud and datacenter systems. This session will explore both projects’ design philosophies, secure boot mechanisms, and approaches to improving trust through open-source development.
	Panel Discussion \| RISC-V Association Japan This panel will reexamine the significance of the Linux-class RISC-V platform defined by RVA23. While the standardization of ISA extensions continues to advance, it is the standardization of non-ISA domains—such as I/O, memory, networking, and coherence—that will ultimately determine implementation interoperability. The session will explore the current state and challenges of platform standardization within the RISC-V ecosystem from both hardware and software perspectives.
	Activities of RISC-V Working Group of JASA RISC-V Working Group \| Japan Embedded Systems Technology Associations (JASA) \| In recent years, the JASA RISC-V Working Group, efforts have focused on promoting understanding of RISC-V and validating implementation technologies. The group first implemented a RISC-V processor on FPGA, followed by a prototype chip fabricated through the Google Shuttle program, on which functional demonstrations and software evaluations were conducted. Currently, the group is developing an original in-house RISC-V chip design, achieving successful demonstrations at each stage. This presentation will highlight these achievements and discuss future development plans.
	Hands-on Tutorial and Demo: OpenROAD and Tiny Tapeout Workflow \| ISHI-Kai This hands-on tutorial uses the open-source EDA tool OpenROAD and the educational Tiny Tapeout platform to guide participants through the fundamental workflow from LSI design to chip fabrication. Participants will gain practical experience with design automation, physical implementation, and verification processes by performing each step interactively. The goal is to provide a hands-on understanding of open-source hardware design methodologies. (Advance registration is recommended.)