RISC-V Day Tokyo 2025 Autumn Tutorial “Building a Device ‘ID Card’—From Power-On to Tamper Detection and Remote Proof (Tentative Title)” :RISC-V Day Tokyo 2025 Autumn • Instructor: H. Andrés Lagar-Cavilla, Principal Engineer, Google)

9/29/2025

FOR IMMEDIATE RELEASE

“Building a Device ‘ID Card’—From Power-On to Tamper Detection and Remote Proof (Tentative Title)”

(RISC-V Day Tokyo 2025 Autumn • Instructor: H. Andrés Lagar-Cavilla, Principal Engineer, Google)

Subhead

We’ll emphasize how it works rather than the Caliptra name: a 90-minute, plain-language, demo-driven tutorial on proving that servers and embedded devices are trustworthy and safe.

Tokyo — Thursday, December 4, 2025 (JST)

RISC-V Day Tokyo will host an introductory tutorial led by H. Andrés Lagar-Cavilla, a Principal Engineer at Google working on platform security and systems software. Rather than foregrounding the “Caliptra” brand, this session explains the role and construction of a device Root of Trust—the mechanism that acts as a device’s ID card—using concrete examples and live demos.

Who should attend: Hardware/software engineers for servers and embedded systems; FW/OS/security practitioners; students

What to bring: Laptop recommended (view-only is fine)

Registration URL：https://riscv-day-2025-autumn.peatix.com/view

First things first: what this technology does (substance over name)

  • Impersonation prevention: Show that the device is genuine and has not been swapped after shipment.

  • Tamper detection: On boot, verify that software carries a valid signature; if not, halt boot.

  • Third-party proof: Send evidence (certificates + measurements) to a cloud or management server proving the device is in a safe state.

  • Built for real operations: Prepare, before mass deployment, to keep running safely during updates and faults (e.g., key custody & authorization, signed updates, safe rollback, audit-quality logs).

Examples: datacenter servers, manufacturing equipment, network appliances, BMCs, automotive ECUs, home gateways, and more.

Outcomes (what you’ll be able to do afterwards)

  • Explain the end-to-end flow: Power-on → secure boot → measurements → attestation → service access.

  • Run a minimal trial: Know the required parts, how to handle keys, and verification steps.

  • Avoid common pitfalls: Take away concrete fixes for key management, update design, and audit/inspection gaps.

Session flow (90 minutes)

  1. Root-of-Trust basics & design checkpoints (15 min)

  2. Demo: from first boot to remote proof (25 min)

  3. Integration & operations: updates, key rotation, incident first steps, rollback, audit logs (25 min)

  4. Q&A (25 min)

    Handouts: checklist, minimal starter bill-of-materials, reference links, and a mini-glossary

Reference: organizations involved in the Caliptra project (public info)

  • Founding companies: AMD, Google, Microsoft, NVIDIA

  • Hosts / standardization venues: Open Compute Project (OCP) for specifications; CHIPS Alliance (Linux Foundation) for open-source IP/ROM/FW and docs

  • Community contributors (examples): 9elements, AMI, Antmicro, ASPEED, Axiado, Lubis EDA, ScaleFlux, Marvell, Nuvoton, and others

  • Integrators publicly noted: AMD, ASPEED, AXIADO (Caliptra 1.x integration recognized by CHIPS Alliance)

  • Volume adoption signals: Google and Microsoft for in-house cloud silicon; AMD for server products (per OCP documents)

Note: This list describes Caliptra project participation and is separate from event sponsors. It reflects 2024–2025 public statements; check OCP/CHIPS Alliance and company releases for updates.

Instructor quote

“We’ll keep jargon to a minimum. Step by step we’ll unpack what is happening, and you’ll leave with procedures and checkpoints you can run inside your company tomorrow.”

— H. Andrés Lagar-Cavilla (Google / OCP Incubation Committee, Security)

Technical note: what “Caliptra” means here

Caliptra is an effort to provide the above Root-of-Trust as open specifications and implementations. This tutorial focuses on design and operational essentials—using Caliptra as a worked example—but frames them as general principles you can apply even with other approaches.

Event details

  • Date: Thursday, December 4, 2025 (JST)

  • Venue: Tokyo, Japan (full program to follow)

  • Registration: [Insert URL]

  • Press & sponsors: Media kit and demo opportunities available on request

Speaker bio (short)

H. Andrés Lagar-Cavilla is a Principal Engineer at Google focusing on platform security and core systems. He has led Google-wide mitigations for Meltdown/Spectre, production kernel and memory-management work, and Google Compute Engine memory management. He serves on the OCP Incubation Committee (Security), previously co-founded the virtualization startup GridCentric, worked at AT&T Labs—Research, and earned his Ph.D. at the University of Toronto (awards include the NSERC Doctoral Prize and EuroSys Best Paper).

Contact

RISC-V Day Tokyo Secretariat (Attn: Shumpei Kawasaki)

shumpei.kawasaki@swhwc.com

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