According to research firm Semico, RISC-V machine learning (AI) system-on-chips are expected to maintain a compound annual growth rate (CAGR) of 73.6% and ship a cumulative total of 25 billion units until 2027. Will be. “RISC-V Days Tokyo 2022 Spring” to be held from May 31st to June 2nd, 2022 is the largest RISC-V event in Japan. Nearly 30 organizations promoting “semiconductor crustal movements” with RISC-V as the epicenter will give a lecture.
This article publishes the contents of the program in advance of the press release on April 18th.
Date and method:
May 31st (Tuesday) 13: 00-17: 00 (Japan time)
June 1st (Wednesday) 10: 00-15: 00 (Japan time)
June 2 (Thursday) 10: 00-15: 00 (Japan time)
It will be held online via online distribution by Vimeo.
Registration site: https://peatix.com/event/3177358/view
Conference information site: https://riscv.or.jp/risc-v-days-tokyo-2022-spring/
Program contents
DAY 1: May 31, 2022 (Tuesday) / 12: 50-19: 00 JST (GMT + 9) Speaker (honorific title omitted) and lecture content
Please note that the speakers and contents are subject to change, and the time may change on the day of the event due to various reasons.
Time Language Presentation Title Presenter | Affiliation Institution Lecture Material
12: 50-13: 00 Question method at the Japanese-English conference and introduction of the online RISC-V pavilion # day1_01_intro
13: 00-13: 15 Japanese-English Day 1 Welcome words # day1_02_welcome
Makoto Ikeda | Graduate School of Engineering, The University of Tokyo Electrical Engineering
13: 15-14: 00 Sun SiFive Update “The future of RISC-V has no limits.” # Day1_03_dts
Atsushi Ishii | SiFive, Inc. Japan Representative
Yoshito Kondo | General Manager, LSI Design Service Department, DTS Insight Co., Ltd.
14: 00-14: 30 Development of RISC-V processor realized by ASIP Designer and enhancement using existing RTL # day1_04_synopsys
Mitsuru Banno | Japan Synopsys GK Technology Headquarters Solutions Group, Processor & Security IP Solutions Staff / Application Engineer
14: 30-15: 00 Sun MIPS RISC-V and Its Use Cases day1_05_mips
Michio Abe ｜ MIPS Tech, Solutions Architect
15: 00-15: 30 Sun GD32VF103 Introduction of RISC-V built-in MCU # day1_06_gigadevice
Kenji Kageyama | Giga Device Japan, Marketing Director
15: 30-16: 00 Day Efinix FPGA and Uno Lab 1-stage RISC-V for ultimate power efficiency # day1_07_efinix
Ikuo Nakanishi | Efinix Country Manager
Makoto Fukushima / Uno Lab Co., Ltd. / Representative Director
16: 00-16: 30 RISC-V compatible Imperas high-speed instruction set simulator utilization day1_08_esoltrinity
Shuzo Tanaka | Esol Trinity Co., Ltd. Director and General Manager of Engineering Department
16: 30-17: 15 High-quality RISC-V verification environment using Imperas DV and the new open standard RVVI
# day1_09_imperas
Shuzo Tanaka | Esol Trinity Co., Ltd. Director and General Manager of Engineering Department / Imperas Software Ltd.
17: 15-17: 45 Day Kodaship’s custom RISC-V solution # day1_10_codasip
Takaaki Akashi ｜ Codasip Group, Japan Country Manager
17: 45-18: 15 A software development environment that seamlessly supports RISC-V evaluation, development, and functional safety support.
# day1_11_iar
Naoki Matsuda | IAR Systems Co., Ltd. Sales Department Account Manager
18: 15-18: 45 English Imagination Catapult: The RISC-V CPU Cores # day1_12_imagination
Naresh Menon ｜ Imagination Technologies, Director of Product Management
18: 45-19: 00 Japanese-English Day 1 Closing Declaration Online RISC-V Pavilion Program Introduction # day1_13_closing
RISC-V Association
DAY 2: Wednesday, June 1, 2022 / 10: 00-16: 00 (GMT + 9) Speaker (honorific title omitted) and lecture content
Please note that the speakers and contents are subject to change, and the time may change on the day of the event due to various reasons.
Time Language Presentation Title Presenter | Affiliation Institution Lecture Material
10: 00-10: 05 How to ask questions at the Japanese-English conference and introduction of the online RISC-V pavilion # day2_01_intro
10: 05-10: 40 days Keynote Lecture: RISC-V: The Open Era of Computing (tentative title) # day2_02_welcome
Calista Redmond | RISC-V International
10: 40-11: 20 English Keynote Lecture: Siemens EDA Software, Hardware and Tools (tentative title) # day2_03_siemanseda
Siemens EDA
11: 20-12: 00 English Keynote: Siemens EDA Tool (tentative title) # day2_03_siemanseda2
Siemens EDA
12: 00-13: 00 DAY 2 RISC-V Online Pavilion
13: 00-13: 30 Sun New RISC-V Book Japanese Translation “Digital Design and Computer Architecture, RISC-V Version”
A New RISC-V Book Japanese Translation “Digital Design and Computer Architecture, RISC-V Edition” (tentative title) # day2_05_keio
Hideharu Amano | Professor, Faculty of Science and Technology, Keio University
13: 30-14: 00 Sun AI Edge Contest –Car driving image recognition using RISC-V # day2_06_signate
Atsushi Nishi | SIGNATE Co., Ltd. Data Scientist
14: 00-14: 30 Sun Previews of JASA ’s 2022 Conferences in Osaka and Tokyo and New Semiconductor Design Training Courses # day2_07_jasa
Kobiyama Tomohisa | Japan Embedded System Technology Association
14: 30-15: 00 English RISC-V Linux Platform Projects 2022 (tentative title) # day2_08_redhat
Wei Fu | Red Hat Software (Beijing) Co., Ltd. Senior Software Engineer
15: 00-15: 30 English Introduction to the Codasip University Program
(Introduction of Codasip University Program) # day2_09_codasip
Keith Graham | Head of University, Codasip
15: 30-16: 00 Day 2 Closing Declaration Online RISC-V Pavilion Introduction Day 3 Program Introduction # day2_11_closing
RISC-V Association
16: 00-17: 00 X DAY 2 RISC-V Online Pavilion
DAY 3: June 2, 2022 (Thursday) / 10: 00-16: 00 JST (GMT + 9) Speaker (honorific title omitted) and lecture content
Please note that the speakers and contents are subject to change, and the time may change on the day of the event due to various reasons.
Time Language Presentation Title Presenter | Affiliation Institution Lecture Material
10: 00-10: 05 How to ask questions at the UK-Japan conference and his online RISC-V pavilion introduction # day3_01_intro
10: 05-10: 30 Days Recent activities of AI chip design base and post-Moore semiconductor technology # day3_02_aist
Kunio Uchiyama | AI Chip Design Center (AIDC) Director / National Institute of Advanced Industrial Science and Technology (AIST)
10: 30-11: 10 English Latest Statistics from Google ’s No Cost Shuttle Program # day3_03_google
Tim Ansell, | Google, Software Engineer
11: 10-11: 50 English 45 Chips in 30 Days: Open Source ASIC at its best! (Draft title) # day3_04_efabless
Mohamed Kassem, Chief Technology Officer | eFabless.com (USA)
11: 50-12: 20th Evaluation of Google \ eFabless Open Source EDA / PDK / IP Program (Draft title) # day3_05_toshiba
Jiro Amenomiya | Toshiba Corporation Cyber Security Technology Center (planned)
12: 20-13: 20 Japanese-English DAY 3 Online RISC-V Pavilion
13: 20-13: 50 UK International Collaboration Opportunities on Semiconductor e.g. Need for No-Cost Shuttle Program amongst Universities and Research Labs in Vietnam # day3_06_vnu
Xuan-Tu Tran | Vietnam National University Hanoi (VNU), Director of Information Technology Research Institute (ITI) (Vietnam)
13: 50-14: 30 UK International Collaboration Opportunity amongst Universities and Research Labs in Asia leveraging No-Cost shuttle # day3_07_iit
Veezhinathan Kamakoti | Director, Indian Institute of Technology-Madras
14: 30-15: 00 Sun Designing an Economically Viable SoC using open source EDA, PDK and IPs –Google ’s no-cost shuttle to eFabless shuttle onward # day3_08_shc
Shumpei Kawasaki | SH Consulting K.K .. Kesami Hagiwara, Pham Cong-Kha | University of Electro-Communications
15: 00-15: 30 English From Zero to ASIC on OpenRoad and OpenLane (Draft title) # day3_09_zerotoasic Matt Venn | ZeroToASIC
15: 30-16: 00 Declaration of termination RISC-V Days Autumn introduction
# day3_10_closing
RISC-V Association Online RISC-V Pavilion
The online RISC-V pavilion is a livestream show of the demo. You can also ask questions to the demonstrators, which is a great opportunity to gain a deeper understanding of the technical content.
Please note that the speakers and contents of the online RISC-V pavilion are subject to change.
Date / Time Language Content Announcement Company / Organization Demonstration Material
June 1, 12: 00-13: 00, 16: 00-17: 00, June 2, 12: 20-13: 20
Google Chip EDA Demonstration
Johan Euphrosine | Google (USA)
June 1, 12: 00-13: 00, 16: 00-17: 00
June 2, 12: 20-13: 20
DTS Insights Booth DTS Insights
June 1, 12: 00-13: 00, 16: 00-17: 00
June 2, 12: 20-13: 20
Marmot IoT Demonstration: Sensor Actuator Leaf, Energy Harvesting Aggregator, and Cloud Service
Hoan Huynh Vu | SH Consulting Viet Nam (Viet Nam)
RISC-V Days First Platinum Partner Introduction
Siemens EDA was one of the first to pay attention to “domain-only architecture”. Cloud service providers such as GAFA will design and manufacture “domain-only architecture” such as search engine page rank mechanism, data center AI processing, video transcoding required for video broadcasting, smartphone processor, etc. in-house. became. Siemens EDA provides EDA for cutting-edge processes that are essential for such system-on-chip semiconductor design.
Imperas is an innovative company that provides the processor “verification technology” as a commercial design environment, which has been a secret technology such as Intel and ARM for a long time. For open architectures such as RISC-V, we offer essential architectural technologies as products.
With DARPA support, Google provides OpenROAD, OpenLane, an open source design tool (EDA), an open source process development kit (PDK), and an open source intellectual property (IP) to “democratize” semiconductor design prototypes. We are promoting the business to do. Under the manifesto of “Open source up to the last 1 nanometer”, we provide an open source design environment that allows companies, universities, and individuals to easily make semiconductors without making a large investment.
eFabless is a pioneer in open source EDA tools such as OpenLane, while offering a revolutionary service called Chip Ignite that can run a prototype shuttle for $ 10,000 US dollars on a 130-nanometer process.
International cooperation on semiconductors with Japan’s neighboring countries is also becoming more important. In addition to the cooperation that makes big news, international cooperation with academia and companies as blocks is also attracting attention.
On March 19th, Prime Minister Kishida visited India. It is said to be to strengthen “bilateral” relationships in order to overcome geopolitical challenges. It is important to establish a “bilateral” relationship with neighboring countries even in open source software and hardware represented by RISC-V. This time, we would like to invite people who are educating software and hardware in Asia, such as Indian Institute of Technology (IIT) and Vietnam National University Hanoi (VNU), to exchange opinions.
event name:
RISC-V Days Tokyo 2022 Spring
RISUKU~FAIBU DEIZU TOUKYO 2022 Spring
SNS:
Web: https://riscv.or.jp/
Twitter: @riscv_a
Slack: https://risc-v-association.slack.com
Facebook: https://www.facebook.com/riscv.a
partner:
platinum
Siemens EDA (Siemens Digital Industries Software: USA)
Imperas Software Ltd. (UK)
Google (Google LLC: USA)
eFabless (eFabless Corporation: USA)
DTS Insight Co., Ltd. (Japan)
SH Consulting Co., Ltd. (Japan)
Silver
SIGNATE Co., Ltd. (Japan)
GigaDevice Semiconductor (China)
Esol Trinity Co., Ltd. (Japan)
Imagination Technologies (UK)
Efinix, Inc. (USA)
Codasip (Headquarters Germany)
MIPS Tech, LLC (USA)
Sponsor:
RISC-V International (RISC-V International: Switzerland), Embedded Systems Technology Association (Japan), Indian Institute of Technology-Madras
Call for general presentations: Scheduled to be adopted in mid-May. https://riscv.or.jp/en/risc-v-days-tokyo-2022-spring-en/cfp
Organizer: RISC-V Association
Office location, phone number, zip code, person in charge:
〒104-0061 7-18-13-502, Ginza, Chuo-ku, Tokyo
Shunpei Kawasaki (Chairman)
Yasuyuki Saito (Secretariat)
Phone: 03-5565-0556, E-mail: yasuyuki <dot> saito <at> riscv <dot> or <dot> jp
RISC-V AI SoC Rapid Growth:
RISC-V AI SoC will maintain a compound annual growth rate (CAGR) of 73.6% by 2027, with cumulative shipments of 25 billion units predicted by Semico “RISC, SoC, AI, and RISC for design initiation” -From “V CPU Market Analysis” (CC330-21)
Exhibitor: https://riscv.org/blog/2022/02/semico-researchs-new-report-predicts-there-will-be-25-billion-risc-v-based-ai-socs-by-2027/
A new report from Semico Research predicts that there will be 25 billion RISC-V-based AISoCs by 2027. Rich Warginiac Semico Research Corporation
The survey highlights the momentum of the current RISC-V architecture and highlights the remarkable growth in the consumer, enterprise and telecommunications markets.
RISC-V is leading the open era of computing across the consumer and enterprise markets. In Semico Research’s latest report, “Analysis of the RISC-V CPU Market for SIP, SoC, AI, and Design Launch” (CC330-21), which focuses specifically on the implementation of artificial intelligence (AI), the company is RISC. -Forecasting current investment in V. The architecture will continue to grow as the market increasingly witnesses more open source designers providing the power of open source design. High-level insights show significant market revenue growth of 9.0% for semiconductor intellectual property (SIP) as a whole and 9.8% for the CPU SIP market. At the same time, RISC-V CPU SIP will experience a CAGR of 34.9% by 2027.
Over the past year, many organizations have deepened their RISC-V strategy and leveraged the capabilities of open RISC-VISA to create custom core and SoC designs. In fact, Semico Research predicts that by 2027, 25 billion RISC-V-based AI SoCs will hit the market with $ 291 billion in revenue for the same year. Incorporating AI into silicon solutions for all types of applications is a powerful driver in today’s semiconductor market, and RISC-V growth is expected in many major industries. This is expected to be 57.2% for low-end smartphones, 112.3% for 5G infrastructure, 68.9% for data centers, 78% for PCs and game consoles, 313.8% for cellular infrastructure, and 85.2% for consumer IoT within the next five years. Includes growth rate. .. These various market segments and end-application growth rates represent a combination of AI-SoC utilizing RISC-V that acts as an accelerator and main CPU, and / or other components with systems that require CPU functionality. I am.
The RISC-V architecture impresses SoC designers and architects. Most of the design, revenue, and shipments come from AISoCs that use the RISC-V architecture over the next few years.
The report also reviews the fast-growing silicon IP market. Semico Research predicts that RISC-V’s SIP market revenue will increase by approximately 36.9% from 2021 to 2022. Note that this move is the result of many companies using RISC-V instead of other traditional CPU SIP types.
The RISC-V community has made breakthroughs in developing extensions and specifications to meet the latest computing requirements in order to accelerate RISC-V adoption in various market segments. In December 2021, RISC-V announced 15 new extensions and approved the vector, scalar encryption, and hypervisor specifications. This helps to bring new opportunities for developers creating RISC-V applications such as AI, ML and IoT.
In Semico Research’s RISC-V CPU Market Analysis for SIP, SoC, AI, and Design Launch, the RISC-V ecosystem is adopting and designing and developing in the SoC market for consumer, enterprise, and communications applications. Explains how to keep expanding. You can purchase and download the full report of Semico Research here for further reading of RISC-V analysis and forecasts.
“Incorporating AI into silicon solutions for all types of applications adds a powerful impetus to today’s semiconductor market,” said Rich Wawrzyniak, Principal Analyst for Semico ASIC and SoC Research. “In every sense, the RISC-V architecture impresses SoC designers and architects. Most of the design, revenue, and unit shipments will be AI that will use the RISC-V architecture in the coming years.
Brought by SoC. “.
Other RISC-V, AI SoC information:
AI SoC revenue is expected to reach $ 291 billion by 2027.
Shipments of AI SoC units are expected to reach 25 billion by 2027.
Revenue in the SIP market will increase to 6.7 billion dollars (871.6 billion yen) in 2020, an increase of 9.8% from 2019.
The CPU SIP market will increase by 12.8% in 2020 to reach 2.2 billion dollars (290 billion yen).
