The entire ESP32 new generation chip lineup, start shipping in 2021 from Espressif, a pioneer of MCUs for wireless IoT, is expected to be equipped with one RISC-V CPU in some form. ESP32 uses the same TSMC’s 40nm process as the previous generation products. Below are the lineups as currently known.
Sensor IoT ESP32-C3: The main processor is one RISC-V CPU. No low power consumption processor.
Camera IoT ESP32-S2: The main processor is one Xtensa CPU. One RISC-V CPU as a low power consumption processor.
Image Processing IoT ESP32-S3 (estimated): The main processor is two Xtensa CPUs. One RISC-V CPU as a low power consumption processor.
ESP32-S3 is expected to be announced in 2021. We are estimating that it will be equipped with 2 Xtensa CPUs + 1 RISC-V. ESP32-C3 working samples are already being distributed. Mass production is expected to start in 2021.
We would like to describesa low power consumption processor. The power domain of the new generation ESP32 is divided into a low-speed processor that includes a real-time clock (RTC) that operates with a clock clock and a high-speed processor that operates at a clock frequency of 160-240 MHz. The feature of the new generation ESP32 is that there is a CPU that operates with a clock clock. In ESP32-S2, RISC-V is used for the low-speed processing section. In ESP32-C3, RISC-V is used for the high-speed processing unit.
It’s a shame, but the feat of the new generation ESP32 is the integration of memory with stacked chips. I think that the ESP32 used to have an external flash and PSRAM. These memories are important because the functionality of a computer is basically determined by its memory capacity. With laminated chips, the form factor of the final ESP32 system is surprisingly low. It can also be used for wearables.
Multi-Die Chip ESP32-S2-FH4: 2MB flash memory (Flash NOR) integrated
Multi-Die Chip ESP-S2-FN4R2: 2MB flash memory (Flash NOR) and 4MB pseudo static RAM (PSRAM) integrated
Multi-Die Chip ESP32 FEATERSF2: 16MB flash memory (Flash NOR) and 8MB pseudo static RAM (PSRAM) integrated
Notice: RISC-V Days Tokyo 2020 Spring (April 22-23, 2021). This year’s focus area is (1) open source EDA tools and his process development kit, (2) RISC-V CPU from Japan, and (3) RISC-V products that are appearing one after another.