“Japan’s Semiconductor Strategy 2024+1/2– A Cluster of AI Chip Companies Taking on NVIDIA”
Rapidus’ challenge, NVIDIA’s leadership, and the future of the semiconductor industry symbolizing the AI era. Be sure to pick up this guidebook to ride this wave of innovation.
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[Main themes]– The future of AI and semiconductors
– Lapidus’s challenge in manufacturing 2nm semiconductors
– The origins of NVIDIA’s AI semiconductor technology
– NVIDIA, Lapidus, and the roadmap to future semiconductors
– Painting the future of AI and semiconductors: Using NVIDIA as an example, we explore the 21st century innovation process brought about by technology and co-creation.
– For investors and policymakers: Includes extensive information on semiconductor-related stocks and government support measures.
– A reference for career development: A path to becoming an engineer in the semiconductor industry.
– NVIDIA’s unique evolution of AI chips and CUDA platform over the past 20 years.
– The secrets of the leadership and management philosophy of NVIDIA’s Jensen, a leader in the semiconductor industry.
– New AI market trends and innovative AI technologies that AMD and 15 startups are taking on.
– The potential for international cooperation and technological innovation centered around NVIDIA and Rapidus.
– Responding to the geopolitical risks brought about by the US-China conflict.
Challenge 1: Establishing technological capabilities
GAA (Gate-All-Around) transistors, backside power distribution (BSPD), and yield rate
Challenge 2: Playing a part in the global semiconductor supply chain
Shifting from a vertically integrated model to a horizontal division of labor model
Issue 3: Semiconductor human resource development and fund raising
Lack of human resources to support advanced manufacturing technology and long-term funding plans
Challenge 4: Global competition How to compete with leading companies like TSMC and Samsung?
Topic 5: Policies and funding mechanisms to support technological innovation
Analyze the factors that will determine the success or failure of the AI semiconductor support policy announced by Prime Minister Ishiba.
Hardcover: 492 pages (147 x 209 mm)
Price: 2,000 yen (excluding tax)
Editor: Taho Haruyuki, Supervisor: Tanabe Izumi, Binding: Nakajima Takayuki
Release date: November 1, 2024, 1st edition, 1st printing
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For more information, please contact Nishimura Shoten Co., Ltd., a wholesaler specializing in natural science books. Publisher: Shunpei Kawasaki
Published by: Sohaco Publishing Co., Ltd.
Recommended by: RISC-V Association
7-18-13, Ginza, Chuo-ku, Tokyo
Tel: 03-5565-0556, Main: 03-3833-3717
Email: sohaco@swhwc.com
Book code: ISBN 978-4-91109-09-2
Category code: C0034
Price: 2000 yen + tax
Published by: Sohaco Publishing Co., Ltd.
Technology B2-53 Hardware Development
Computer Architecture B8-02
Deep Learning
[Table of Contents]
• Preface vii
1. Japan’s Semiconductor Strategy and RAPIDUS: Integrating Diplomacy, Security, and Economic Policies 1
1.1 Why 2nm Do we need fabs? 1
1.1.1 Competitive reset effect of new technology introduction 1
1.1.2 Introduction of GAA transistor technology 2
1.1.3 EUV (extreme ultraviolet) lithography technology 3
1.1.4 Backside power distribution (BSPD) technology 3
1.1.5 New partnerships and access to manufacturing facilities 3
1.1.6 Common learning curve for established companies and new entrants 4
1.1.7 Riding the timing of a paradigm shift 4
1.2 65-year history of MOSFET (metal-oxide-semiconductor) 4
1.2.1 Japanese companies withdraw from the development race with planar MOSFET 6
1.2.2 FinFET deployment globally 8
1.2.3 FinFET developed from the idea of Japanese engineers 9
1.2.4 Japanese engineers who followed FinFET (2014) 10
1.2.5 Transition to GAA (Gate-All-Around) at 2nm (2024) 11
1.2.6 Is GAA an evolution rather than a revolution from FinFET? 12
1.3 “Next-generation technologies” associated with the 2nm process 15
1.3.1 Improve performance and area with backside power delivery (BSPD) 16
1.3.2 Through-silicon via (TSV) 17
1.3.3 Intel has already completed backside power delivery at 2nm 18
1.3.4 Intel also discloses backside power delivery wafer manufacturing method 19
1.3.5 Intel predicts that backside power delivery will not increase costs 20
1.3.6 Increased use of EUV for 2nm frontside power delivery (FSPD) 20
1.3.7 Intel says backside power delivery will not degrade yields 21
1.3.8 Through-silicon vertical electrical interconnects are necessary for 3D stacking 21
1.3.9 Interposers are essential for 2.5D stacking 22
1.3.10 Intel and AMD develop their own chiplets 22
1.3.11 Intel’s proprietary chiplet technology “Foveros” 23
1.3.12 AMD also develops its own chiplet technology 25
1.3.13 Chiplet technology at NVIDIA 28
1.3.14 Chiplet interoperability and standardization 30
1.3.15 UCIe (Universal Chiplet Interconnect Express) 31
1.3.16 AIB: Advanced Interface Bus (2018) 32
1.3.17 10 companies dominating Die-to-Die (D2D) standards 33
1.3.18 The business of selling chiplets 35
1.3.19 Alpha Wave Semi’s chiplet business 36
1.3.20 3D and 2.5D stacking technology and backside power supply 36
1.3.21 Extreme ultraviolet lithography (EUV) at advanced nodes 37
1.4 TSMC’s status of 2nm and beyond 40
1.4.1 TSMC’s EUV adoption status 40
1.4.2 TSMC’s roadmap for 2nm and beyond: 41
1.5 Samsung 2nm roadmap 43
1.6 Intel’s 2nm roadmap 45
1.7 Rapidus’ 2nm fab 47
1.7.1 The significance of Japan having a next-generation semiconductor fab 47
1.7.2 Rapidus’ 2nm schedule 48
1.7.3 Is the Rapidus 2nm schedule too late? 48
1.8 Eight major industries that make up the semiconductor supply chain 50
1.8.1 EDA (Electronic Design Automation) companies? 50
1.8.2 IP (Intellectual Property) providers 50
1.8.3 Fabless semiconductor companies 51
1.8.4 Semiconductor manufacturing companies (foundries) 51
1.8.5 IDM (Integrated Device Manufacturers) 51
1.8.6 OSAT (Outsourced Semiconductor Assembly and Test) 52
1.8.7 Semiconductor material suppliers companies 53
1.8.8 Semiconductor manufacturing equipment manufacturers 53
1.9 Overview of Japan’s semiconductor strategy 54
1.9.1 Strengthening the semiconductor manufacturing base 54
1.9.2 Semiconductor-related companies entering the market and creating jobs to stimulate the local economy: 54
1.9.3 Quantitative targets for semiconductor revival (achieving 15 trillion yen in sales in 2030) 55
1.9.4 Supplementary budget for semiconductors 56
1.9.5 Enforcement of new law and huge investment: measures to strengthen domestic semiconductor fabs 57
1.9.6 Establishment of new tax system to promote production in the domestic semiconductor industry 60
1.10 Global semiconductor competition 61
1.10.1 Initiatives of major countries 61
1.10.2 Securing next-generation semiconductors 62
1.10.3 Initiatives for manufacturing next-generation logic and memory semiconductors 62
1.10.4 Establishment of cutting-edge semiconductor manufacturing ecosystem 63
1.10.5 Lapidus Co., Ltd. 66
1.10.6 Additional support for Lapidus 67
1.10.7 Lapidus’ future business phase and support 69
1.10.8 Beyond 2nm Semiconductor technology for the next generation 70
1.10.9 Began investment support for cutting-edge semiconductors ahead of the rest of the world 72
1.11 Developing use cases for next-generation semiconductors 73
1.11.1 Hierarchical structure of services in AI and computing 73
1.11.2 Memory and storage strategies 74
1.11.3 Direction of memory for AI calculations 75
1.11.4 Recent efforts toward realizing next-generation semiconductors 77
1.11.5 Rapidus West Coast base (Rapidus Design Solutions) 78
1.11.6 Collaboration with Tenstorrent and Esperanto 79
1.11.7 Why are chiplets needed for next-generation semiconductors? 80
1.11.8 Importance of advanced packaging strategy and efforts 82
1.11.9 Development of advanced packaging technology for advanced semiconductor back-end processing 83
1.12 Leading-edge Semiconductor Technology Center (LSTC) 85
1.12.1 Organization of the Leading Semiconductor Technology Center (LSTC) 85
1.12.2 LSTC research and development projects 86
1.13 Diplomatic benefits of advanced semiconductors 88
1.13.1 Legacy semiconductor industrial support and economic security 88
1.13.2 Survey on legacy semiconductors in the United States 88
1.13.3 Ensuring security in semiconductor-related industries 89
1.13.4 Risks of technology and data leakage and countermeasures 90
1.13.5 International semiconductor cooperation 91
1.13.6 Japan-US summit and Japan-US-Philippines summit 93
1.13.7 The 3rd Japan-US Commercial and Industrial Partners (JUCIP) Meeting 94
1.13.8 Japan-EU semiconductor cooperation 95 1.13.9 Japan-UK semiconductor cooperation 96
1.13.10 Semiconductor cooperation between Japan and the Netherlands 97
1.13.11 Overview of R&D support systems in the US and EU 98
1.14 Financial sustainability of Japan’s semiconductor strategy 100
1.14.1 Contents of the Financial System Subcommittee (held on April 9, 2024) 100
1.14.2 Scale of semiconductor support measures in each country (reflecting tax systems and the latest situation) 101
1.15 Semiconductor strategies in countries around the world 102
1.15.1 Semiconductor support projects in the US 102
1.15.2 TSMC overseas investment and government support: A comparison of countries 104
1.16 Power demand and semiconductors 106
1.16.1 Power demand for data centers 106
1.16.2 Attracting AI data centers (DC) and energy measures 107
1.16.3 AI data center initiatives by general electricity transmission and distribution companies 110
1.16.4 GX Green Transformation Executive Committee 111
1.16.5 Energy supply to support AI and data centers 112
1.16.6 AI data centers and advanced computing resources 113
1.16.7 Optimization of AI computing infrastructure and power consumption management 115
1.17 Semiconductor human resource development 118
1.17.1 Establishment of advanced semiconductor development and human resource development base 118
1.17.2 Strengthening R&D and human resource development through LSTC activities 119
1.17.3 Collaboration with overseas institutions and human resource development 120
1.17.4 Initiatives related to semiconductor human resource development 121
1.17.5 Initiatives for semiconductor human resource development in the Tohoku region 122
1.17.6 Importance of advanced human resource development and specific initiatives 122
1.17.7 Strengthening the supply chain of semiconductor materials 123
1.17.8 LSTC Human Resource Development Working Group (WG) 124
1.17.9 Regional consortiums promoting semiconductor human resource development 126
1.18 Economic ripple effects on local communities 127
1.18.1 Economic ripple effects on Kumamoto Prefecture 127
1.18.2 Semiconductor-related companies entering and investing in Kumamoto Prefecture 128
1.18.3 Prime Minister Kishida, TSMC, and local companies roundtable 129
1.18.4 Economic Security Fund to support semiconductor supply chain resilience 130
1.19 Sources 134
2. NVIDIA’s history: 30 years of trials, challenges, and successes 135
2.1 Trends in NVIDIA sales 135
2.2 Market share of desktop PC GPU cards by company 139
2.3 NVIDIA AI for data centers Semiconductors 140
2.4 References 141
2.5 Collaboration between NVIDIA and Taiwanese semiconductor manufacturing: Success built through cooperation 143
2.5.1 1960s Challenges and changes starting from back-end processing 143
2.5.2 1970s Introduction of front-end technology and application-oriented management strategy 144
2.5.3 1980s Pure-play foundries that changed the semiconductor industry 148
2.5.4 Growth of TSMC 151
2.5.5 Taiwan’s semiconductor manufacturing industry and NVIDIA 153
2.5.6 References 154
3. Graphics and AI revolution: Jensen Huang and NVIDIA’s challenge 155
3.1 NVIDIA and Jensen Huang 155
3.2 NVIDIA Founded 156
3.2.1 NVIDIA Founded (1993) 156
3.2.2 Jensen Huang (Huáng Rénxūn) 156
3.2.3 Co-founders 159
3.3 The Early Days of NVIDIA (1993) 168
3.3.1 Origin of the NVIDIA Name 168
3.3.2 3D Graphics Technology at the Time of NVIDIA’s Founding 171
3.4 First Product: NV1 175
3.4.1 Manufacturing Partnership with STMicro (1995) 175
3.4.2 Microsoft DirectX (1995) 180
3.4.3 For Sega NV2 (1995) 180
3.4.4 Quiet pivot (1996) 181
3.4.5 Cut 50% of staff 182
3.4.6 Closed cafeteria but continued nightly pizza orders 186
3.4.7 NV1 returns piled up to create a monument 187
3.4.8 NVIDIA returns to stealth and restarts 189
3.4.9 Sega internal next-generation console development contest (1996) 191
3.4.10 11 people from Sega of America transfer to Hitachi (1996) 194
3.4.11 What happened to 3dFx (1996) 194
3.4.12 Aftermath of “Black Belt” vs. “.Katana” (1996) 195
3.4.13 The “Bubble Economy” (1992) and the “Arm Length Principle” (1994) 196
3.4.14 A $7 million MOU written on a napkin (1996) 197
3.4.15 Amicable termination of the NV2 development contract with Sega (1997) 199
3.4.16 Dreamcast goes to Imagination (1997) 200
3.4.17 Hitachi Semiconductor faces financial difficulties due to sudden changes in the DRAM market (1996) 201
3.5 From 3D accelerators to GPUs (NV3-NV20) 201
3.5.1 Microsoft promotes DirectX (September 1995) 201
3.5.2 TSMC from NVIDIA’s perspective (1996) 205
3.5.3 NV3: RIVA 128 captures 10-15% market share (1997) 207
3.5.4 NV10: GeForce 256 (1999) named GPU 209
3.5.5 GPU driver source not disclosed (1999) 213
3.5.6 Programmable GPU: NV20: GeForce 3 (2001) 214
3.6 OS development at NVIDIA 217
3.6.1 Size of NVIDIA’s OS development team 218
3.6.2 Why is NVIDIA so enthusiastic about OS development 218
3.6.3 Are 99% of blue screens caused by NVIDIA drivers? 221
3.6.4 Graphics benchmark situation in 2000 223
3.7 NVIDIA’s financials 223
3.7.1 Jensen’s shareholding at NVIDIA’s IPO 224
3.7.2 Debt-free management 224 3.7.3 NVIDIA’s largest shareholders 225
3.8 2000s: Diversification and market dominance 226
3.8.1 Expansion into new markets: data centers, automotive, etc. 226
3.8.2 Major new product generation launches and technology advances 231
3.9 Gaining technological advantage through acquisitions 234
3.9.1 Acquisition of 3dfx Interactive (2000) 234
3.9.2 Acquisition of MediaQ and Tegra series (2003) 235
3.10 Strategic partnerships 237
3.10.1 Sony Playstation 3 (2000s) 237
3.10.2 Microsoft Xbox 360 (2000s) 238
3.10.3 IBM HPC High Performance Computing (2000s) 238
3.10.4 Audi Google Earth Navigation (2000s) 238
3.10.5 NVIDIA orders 20 SH7786 evaluation boards from Hitachi 240
3.10.6 Tesla Motors (2000s) 243
3.11 Steady business expansion behind the scenes of the AI revolution 243
3.11.1 The advent of AI deep learning 243
3.11.2 NVIDIA GPUs become essential for AI research and development 245
3.11.3 NVIDIA GPUs and CUDA democratize AI development 246
3.11.4 Impact on the industry 247
3.12 CUDA Platform 247
3.12.1 The spread of large-scale parallel computing with CUDA 248
3.12.2 CUDA’s parallel computing model 249
3.12.3 Support for processing order and data dependency 249
3.12.4 How parallel processing works in CUDA 249
3.12.5 Memory hierarchy and data transfer 250
3.12.6 CUDA library (parallel computing software stack): 251
3.12.7 CUDA’s contribution to computer science 252
3.12.8 CUDA gives AI researchers wings 253
3.12.9 CUDA transforms industries: from genomics to robotics 254
3.13 The beginning of CUDA: Cg, the C language for graphics 254
3.13.1 What is a programmable shader? 255
3.13.2 History of programmable shaders 255
3.13.3 Development of a unique shader compiler by NVIDIA 256
3.13.4 Market response to NVIDIA shader compiler CG 257
3.13.5 Origin of the word “CUDA” 259
3.13.6 Quantum Leap from CG to “CUDA” 260
3.13.7 GPU development tool “CUDA Toolkit” 261
3.13.8 CUDA debugging tool NVIDIA Nsight 262
3.13.9 GPU documentation and support 262
3.14 Is software a “service that only causes losses” for chip companies? 263
3.14.1 Early Jensen’s view of software 263
3.14.2 Jensen’s criticism of the “SH franchise” 264
3.14.3 What NVIDIA learned from “NV1” at the time 265
3.14.4 Initial opposition to expanding Cg compiler development staff (2003) 266
3.14.5 Engineers’ feelings after the IPO (2003) 267
3.14.6 Linus, Stallman, and open source 267
3.14.7 Recruiting Windows OS developers from NVIDIA 269
3.14.8 Talented engineers from NVIDIA 270
3.14.9 A young Cg compiler engineer fighting alone (2002) 271
3.14.10 Conditions for being called a general-purpose GPU 273
3.14.11 Appealing the ease of GPU programming with CUDA 273
3.14.12 References 274
3.15 Mobilizing researchers to promote NVIDIA 274
3.15.1 Google TensorFlow optimized for NVIDIA 274
3.15.2 Google Cloud integration 275
3.15.3 GPU services provided by Amazon Web Services (AWS) 275
3.15.4 Accelerating AI research with Amazon Machine Images (AMI) 275
3.15.5 Microsoft: Azure Machine Learning integration 275
3.15.6 AI research collaboration with universities 276
3.16 NVIDIA’s cutting-edge AI chip architecture 277
3.16.1 The direction of NVIDIA GPU architecture 277
3.16.2 History of NVIDIA GPU architecture 278
3.16.3 Linking GPU architecture with CUDA 279
3.17 Tensor Core 280
3.17.1 Acceleration of matrix operations 281
3.17.2 Implementation of matrix multiplication (Fused Multiply-Add, FMA) 282
3.17.3 Support for multi-precision operations 282
3.17.4 Cooperation with the Transformer Engine 283
3.17.5 Application areas where the Tensor Core is useful 283
3.18 Hopper architecture 284
3.18.1 Features of the Hopper architecture 284
3.19 Transformer Engine 285
3.19.1 Background of the Transformer architecture 285
3.19.2 Details of the Transformer Engine 285
3.19.3 Applications of the Transformer Engine 286
3.20 Dynamic Programming (DP) 287
3.21 Simultaneous execution of multiple tasks with MIG (Multi-Instance GPU) 287
3.22 NVLink 4.0 accelerates GPU-GPU-CPU transfers 288
3.23 HBM3 memory (High Bandwidth Memory 3) 288
3.24 AI chips challenging NVIDIA 290
3.24.1 “The AI Warring States Period will begin in 2025” 290
3.24.2 Major IT companies enter the battle with their own AI chips 291
3.24.3 AMD pursues CUDA with RDNA and ROCm 291
3.24.4 Intel competes by acquiring Ponte Vecchio, Gaudi, and Mobileye 295
3.24.5 Google replaces NV with TPU for cloud AI 300
3.24.6 Tesla develops self-driving AI chip Full Self-Driving in-house 300
3.24.7 Amazon develops AI chips Trainium and Inferencia in-house 301
3.24.8 Qualcomm takes on mobile and in-vehicle AI chips 301
3.24.9 Apple takes on NVIDIA with M-series GPU 302
3.24.10 Tenstorrent’s “Grayskull” and “Wormhole” 302
3.24.11 Graphcore’s Intelligence Processing Unit 303
3.24.12 Cerebras Systems’ Wafer Scale Engine 303
3.24.13 SambaNova’s Reconfigurable Dataflow Unit 304
3.24.14 Mythic AI’s analog AI Inference chips 305
3.24.15 Groc’s Tensor Streaming Processor 305
3.24.16 Summary of companies challenging NVIDIA 306
3.25 NVIDIA innovations start transforming industries 307
3.25.1 Healthcare and life sciences Industries 307
3.25.2 Autonomous Vehicles and Transportation 308
3.25.3 Manufacturing and Robotics 309
3.25.4 Finance and Banking 309
3.25.5 Financial Risk Management and Compliance Applications 310
3.25.6 Media and Entertainment 310
3.26 References 311
3.27 Conclusion 311
3.28 Musings 311
4. Arm’s New Strategy: Improved Performance, Efficiency, and Area with TSMC-Optimized IP 315
4.1 Trends in Arm Revenues and Shipments 315
4.2 Expansion of Flexible Access 315
4.3 Evolution of Arm Architecture and IP for Embedded Systems 317
4.4 Examples of Embedded Chip Products 320
4.5 Compute subsystems are for specific foundries 320
4.6 References 321
5. TSMC’s 24 years: Sales trends and technology node changes 323
5.1 Trends in TSMC sales 323
5.2 Profits and profit margins 326
5.3 References 327
6. Google-funded shuttle RISC-V prototype with DARPA automated design flow 329
6.1 Realizing MARMOT RISC-V with 1MB+ memory 330
6.2 Good luck with Google’s free shuttle 331
6.3 Efabless’ Caravel Harness 332
6.4 Linux-based IoT edge and RTOS-based IoT edge 333
6.5 Open Road work log (2022) 333
6.6 Software verification of the chip prototyped by Efabless (2024) 335
6.7 MPW-6 demo (August 1, 2024, November 20) 338
6.8 “JASA1 chip evaluation board” for distribution to members (planning stage) 339
6.8.1 Cost image of “JASA1 chip evaluation board” 340
6.8.2 Initialization of Dual and Quad connection with QPI flash (completed) 341
6.8.3 Actual evaluation of QPI flash direct execution performance (in progress) 342
6.8.4 Release of Chisel source code (in progress) 342
6.8.5 Direct execution from QPI flash via cache 344
6.8.6 MPW-7 Marmot is capable of high-speed operation at 50MHz 344
6.8.7 Chisel verification with logic simulation and FPGA 344
6.8.8 MPW-7 Marmot’s PSRAM direct execution function to JASA1 345
6.9 Chisel study group 346
6.9.1 “Starting digital circuit design with Chisel” 346
6.9.2 Verifying Chisel operation on Arty A7 FPGA 347
6.10 Future plans 347
6.11 MPW-8 releases self-developed SH-2 348
6.12 Impressions 349
6.13 Conclusion 349
6.14 Acknowledgements 349
7. Andes grows with RISC-V: The future of Taiwan’s No. 1 IP company 351
7.1 Andes Technology holds 30% share of RISC-V 351
7.2 CPU IP lineup and strategy for 2030 354
7.3 Vision for 2030 361
7.4 References 363
8. Scalable RISC-V for DX provided by Tenstorrent 365
9. From simple microcontrollers to complex multi-core SoCs
– Debugging RISC-V-based chips made easy 391
10. RISC-V and the US-China conflict: Open source cooperation continues beyond the divide 401
10.1 Introduction 401
10.2 Origin and basic characteristics of RISC-V 401
10.2.1 What is an instruction set architecture, ISA? 402
10.2.2 Strategic benefits for companies that control the “instruction set” 404
10.2.3 Why RISC-V emerged 404
10.2.4 Why Google is supporting RISC-V on a large scale 405
10.2.5 40-year history of the RISC instruction set at the University of California, Berkeley 406
10.2.6 Differences between RISC-V’s business model and Arm’s 408
10.2.7 IP revenue and number of design starts surpass Arm (2023) 409
10.2.8 Arm leads RISC-V in fundraising through IPO 410
10.2.9 Arm withdraws Apple’s request to raise license fees 411
10.2.10 Performance comparison of cutting-edge RISC-V and cutting-edge Arm 412
10.2.11 Google and Qualcomm team up to complete Android for RISC-V, which China will also use 413
10.2.12 Bosch, Qualcomm, and Infineon’s RISC-V IP for Automotive 415
10.3 More than 300 companies in China use RISC-V for product development 416
10.3.1 T-Head (Pingtouge) RISC-V “Xuantie” 417
10.3.2 Alibaba “Xuantie” RISC-V system 418
10.3.3 HiSilicon RISC-V “Hi3861” 418
10.3.4 Huawei Hi3861 RISC-V ecosystem 419
10.3.5 StarFive’s RISC-V JH7110 SoC 421
10.3.6 China’s Terapines provides a software/hardware co-design environment 422
10.3.7 Chinese Academy of Sciences “XiangShan” Open RISC-V 423
10.4 Superchip embargo on China and RISC-V 424
10.4.1 US export restrictions on digital semiconductor technology to China 424
10.4.2 Japan’s response to export restrictions 424
10.4.3 China and Taiwan to talk at 2023 European RISC-V Summit 426
10.4.4 US lawmakers request RISC-V export restrictions to Biden administration 426
10.4.5 Export restrictions on open industrial standards are difficult 427
10.4.6 The possibility of export restrictions on RISC-V cannot be denied 428
10.5 Japan’s semiconductor policy regarding RISC-V 429
10.5.1 RISC-V subsidy program led by the Ministry of Economy, Trade and Industry 2018-2023 429
10.5.2 Confirmation of Japan-US economic security and technology cooperation at APEC2023 429
10.5.3 Japan-US small reactor (SMR) cooperation announced immediately after APEC 2023 430
10.6 Creation of Lapidus as an integrated policy of the Japanese government 431
10.6.1 Integrating foreign policy, security policy, and economic policy 432
10.6.2 Strategic partnership between Lapidus and Tenstorrent 433
10.6.3 Expectations of the Japanese and US governments for Lapidus 434
10.6.4 Development of civilian and military dual-use manufacturing technology 435
10.6.5 NVIDIA manufactures military and civilian dual-use AI chips 436
10.6.6 Lapidus and RISC-V CPU and AI chip companies partner 437
10.6.7 Collaboration between Rapidus and Arm user semiconductor manufacturers 438
10.7 RISC-V’s footprint in the semiconductor industry 439
10.7.1 Applying the open source philosophy to hardware design 439
10.7.2 The importance of open architecture in generative AI 440
10.7.3 Qualitative changes in semiconductor talent required by the evolution of electronic technology 440
10.7.4 Democratization of hardware design 441
10.7.5 RISE: Software support strategy for new architectures 442
10.7.6 The US and China compete for hegemony over RISC-V technology 442
10.7.7 Global cooperation through the Big Umbrella philosophy 443
10.7.8 References 446
• About the editors and authors 448
• Afterword 451
